STMicroelectronics L6561D

Overview

L6561D from STMicroelectronics is a transition-mode Power Factor Correction (PFC) controller IC designed for AC-DC front-end stages in electronic lamp ballasts, SMPS, and universal-input adapters. It features 1% precision internal reference voltage (2.5 V @ 25°C), ±400 mA totem-pole gate driver output, micro-power start-up current (50 µA typ.), and integrated zero-current detection with disable function on ZCD pin.

For engineers reviewing the L6561D datasheet, L6561D pinout, L6561D application, or L6561D equivalent, key selection criteria include its 85–265 VAC input compatibility, dynamic/static overvoltage protection (OVP) with 40 µA trigger threshold, transition-mode operation for low THD, and SO-8 package suitability for compact PFC designs requiring high efficiency and standby current reduction.

Technical Context

The L6561D implements a mixed-signal BCD process architecture with an improved multiplier stage enabling stable operation across 85–265 VAC inputs while maintaining <3.7% THD (with reducer). Its error amplifier delivers 60–80 dB open-loop gain and 1 MHz GBW, supporting precise regulation of boosted DC outputs up to 400 V.

Transition-mode control is enforced via zero-current detection on pin 5 (ZCD), with internal hysteresis (0.3–0.7 V) and disable capability below 250 mV. The totem-pole driver (pin 7) provides matched ±400 mA source/sink capability at <2 V dropout, directly driving N-channel MOSFETs or IGBTs without external buffers.

Key Specifications

Pinout & Package

Available in SO-8 surface-mount package (JEDEC MS-012AC, 5.0 × 4.0 × 1.45 mm), optimized for thermal performance (R_{th j-amb} = 100 °C/W) and automated assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PFC controller applications.

Compared with UCC28051DR and FAN7930C, the L6561D uniquely combines transition-mode operation, integrated dual-stage OVP, and ±400 mA gate drive in SO-8 - making it optimal for compact, high-efficiency 60–120 W PFC stages requiring minimal external components and robust fault protection.

Availability

L6561D is available at Aetrix Electronics and suitable for electronic lamp ballasts, universal-input AC-DC adapters, and industrial SMPS requiring stable component supply, long-term lifecycle support, and consistent parametric performance across temperature and input voltage ranges.

Supply support for L6561D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, and microcontroller solutions for industrial, automotive, and consumer markets.

The L6561D belongs to ST's legacy PFC controller product line, engineered specifically for transition-mode boost converters in energy-efficient lighting and power supply applications demanding high power factor and low THD without complex control schemes.

FAQ

What is the minimum input voltage range supported by the L6561D?

The L6561D operates across universal AC mains inputs from 85 VAC to 265 VAC, enabled by its improved multiplier stage and wide VCC operating range (11–18 V). Its transition-mode architecture maintains stable regulation and low THD even at 85 VAC, as verified on the EVAL6561-80 demo board achieving PF >0.999 and THD <2.9% with THD reducer.

How does the ZCD pin function as a disable input?

When the ZCD pin voltage drops to ≤150 mV (typ.), the L6561D enters disabled state, reducing quiescent current to 1.4 mA typical. Releasing the pin allows the internal 70–400 µs start timer to re-enable the controller. This feature enables low-power standby modes in adaptive power supplies without external enable circuitry.

Can the L6561D drive a 500 V MOSFET directly?

Yes - the L6561D's GD pin delivers ±400 mA peak current with <2 V dropout, sufficient to drive common 500 V N-channel MOSFETs (e.g., STP8NA50, STP5NA50) used in boost PFC stages. Layout best practices require short, low-inductance gate traces and local 100 nF decoupling at VCC to ensure clean switching and prevent shoot-through.

What is the accuracy of the overvoltage protection threshold?

The dynamic OVP triggers at 40 µA ±5 µA (35–45 µA), corresponding to ∆V_OUT = R1 × 40 µA. With typical R1 = 1 MΩ, this yields 40 V ±3.5 V overvoltage margin. Static OVP activates at 2.25 V ±0.15 V on the internal comparator, providing redundant protection independent of external resistor tolerance.