STMicroelectronics L6562ADTR

Overview

L6562ADTR from STMicroelectronics is a transition-mode (TM) power factor correction (PFC) controller in SO-8 package, featuring 1% internal reference voltage accuracy (@T_J = 25°C), ultra-low 30 µA start-up current, and ±600/±800 mA totem-pole gate driver with active pull-down during UVLO. It enables IEC61000-3-2-compliant PFC pre-regulators up to 400W for flat TVs, monitors, and high-end AC-DC adapters.

For engineers reviewing the L6562ADTR datasheet, L6562ADTR pinout, L6562ADTR application, or L6562ADTR equivalent, key selection criteria include its proprietary THD-optimized multiplier, digital leading-edge blanking on CS pin, disable function on INV pin, and precise dynamic overvoltage protection triggered at 27 µA.

Technical Context

The L6562ADTR implements current-mode control in transition mode using zero-current detection (ZCD pin) to trigger MOSFET turn-on and a sinusoidal-shaped reference from the multiplier (MULT pin) to shape input current. Its error amplifier (INV/COMP pins) regulates output voltage via a 2.5 V internal reference with 1% tolerance and 60–80 dB open-loop gain.

It integrates a two-step overvoltage protection (OVP): dynamic OVP responds to abrupt load drops by monitoring COMP pin current (27 µA typical trigger), while static OVP activates when the error amplifier saturates under light-load conditions. The gate driver (GD pin) delivers 600 mA source / 800 mA sink with 10–15 V output clamp and <110 ns rise time.

Key Specifications

Pinout & Package

SO-8 surface-mount package (8-pin, 150 °C/W junction-to-ambient thermal resistance).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar transition-mode PFC controller applications.

Compared with UCC28051DR, L6562ADTR delivers superior THD performance and simpler layout via integrated ZCD timing and THD optimizer, while L6562DTR offers backward compatibility with enhanced ruggedness-making L6562ADTR the most cost-effective choice for validated 400 W IEC61000-3-2 designs.

Availability

L6562ADTR is available at Aetrix Electronics and suitable for flat panel TV power supplies, high-efficiency desktop PC SMPS, and 400 W AC-DC adapters requiring stable component supply, consistent parametric performance, and long-term production continuity.

Supply support for L6562ADTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for automotive, industrial, and consumer markets.

The L6562ADTR belongs to ST's legacy PFC controller product line, engineered specifically for cost-sensitive, high-volume transition-mode PFC applications in IEC61000-3-2-compliant switch-mode power supplies up to 400 W.

FAQ

What is the purpose of the ZCD pin, and how is it used in transition-mode operation?

The ZCD (Zero-Current Detection) pin senses the demagnetization of the boost inductor via an auxiliary winding or R-C network connected to the MOSFET drain. A negative-going edge on ZCD triggers MOSFET turn-on, ensuring operation precisely at the inductor current zero-crossing - the defining characteristic of transition-mode control that minimizes switching losses and EMI.

How does the L6562ADTR implement overvoltage protection without external components?

L6562ADTR uses dual internal OVP mechanisms: dynamic OVP monitors current flowing into the COMP pin - exceeding ~27 µA forces gate shutdown; static OVP detects error amplifier saturation under light loads. Both reduce quiescent current to <2.2 mA and require only the standard output voltage divider (R1/R2), eliminating external comparators or timers.

Can the L6562ADTR operate without an auxiliary winding on the boost inductor?

Yes - the ZCD pin can be driven directly from the MOSFET drain using a series R-C network (e.g., 330 kΩ + 22 pF). This transfers high-frequency drain edges to ZCD, arming and triggering the zero-current comparator. ST confirms this method works reliably even with small differences between peak input voltage and 400 V output.

What design advantage does the THD optimizer circuit provide compared to standard TM controllers?

The THD optimizer adds a controlled positive offset to the multiplier output near AC line zero-crossings, increasing MOSFET conduction time when input voltage is low. This reduces the conduction dead-angle caused by bridge rectifier reverse recovery and high-frequency filter capacitance, lowering measured THD by up to 3–5 percentage points in real-world 90–264 VAC applications.