STMicroelectronics L6562ATDTR

Overview

L6562ATDTR from STMicroelectronics is a transition-mode (TM) power factor correction (PFC) controller in SO-8 package, designed for high-efficiency AC-DC pre-regulators. It delivers 1% internal reference voltage accuracy (@T_J = 25 °C), ultra-low 30 µA start-up current, and integrated totem-pole gate driver with ±600/±800 mA sourcing/sinking capability-enabling direct drive of high-current MOSFETs in street lighting and IEC61000-3-2-compliant flat-panel TV power supplies.

For engineers reviewing the L6562ATDTR datasheet, L6562ATDTR pinout, L6562ATDTR application, or L6562ATDTR equivalent, this controller offers verified THD optimization circuitry, digital leading-edge blanking on CS pin, disable function via INV pin, and dual-stage overvoltage protection-critical for energy-efficient, outdoor-rated PFC designs operating across -40 °C to +150 °C junction temperature range.

Technical Context

The L6562ATDTR implements current-mode control in transition mode using a proprietary multiplier with linear gain (0.32–0.47 V/V) and dedicated THD optimizer that injects positive offset near line zero-crossings to reduce conduction dead-angle. Its error amplifier features 60–80 dB open-loop gain and 1 MHz GBW, enabling stable voltage loop compensation with external R-C networks between COMP and INV pins.

Operation relies on ZCD pin sensing boost inductor demagnetization for zero-current turn-on, CS pin with 100–300 ns leading-edge blanking for noise-immune current sensing, and dual OVP: dynamic (27 µA trigger) for load-dump events and static (COMP saturation detection) for light-load overvoltage-both reducing quiescent current to ≤2.2 mA during fault.

Key Specifications

Pinout & Package

SO-8 surface-mount package (8-pin, 150 °C/W junction-to-ambient thermal resistance), compliant with JEDEC MS-012AC.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar transition-mode PFC controller applications.

Compared with UCC28051DR and L6562DTR, the L6562ATDTR uniquely combines transition-mode operation, integrated THD optimization, ultra-low start-up current, and dual OVP-making it the only option qualified for outdoor-rated, sub-10% THD, and <0.5 W standby PFC designs below 400 W.

Availability

L6562ATDTR is available at Aetrix Electronics and suitable for street lighting, flat-panel TV power supplies, and IEC61000-3-2 desktop PC SMPS requiring stable component supply, long-term lifecycle support, and traceable sourcing for industrial OEM programs.

Supply support for L6562ATDTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, and automotive ICs with vertical manufacturing capabilities and ISO/TS 16949-certified processes.

The L6562AT belongs to ST's high-voltage analog PFC controller product line, engineered specifically for energy-efficient, thermally robust AC-DC conversion in outdoor, industrial, and consumer applications demanding IEC61000-3-2 compliance.

FAQ

What is the purpose of the THD optimizer circuit in the L6562ATDTR?

The THD optimizer circuit injects a controlled positive offset into the multiplier output near AC line voltage zero-crossings, reducing conduction dead-angle and minimizing crossover distortion in the input current waveform. This lowers total harmonic distortion-typically below 10% at full load-even with wide-range mains input and minimal EMI filter capacitance, as confirmed in ST application note AN3122.

How does the dual-stage overvoltage protection operate?

Dynamic OVP triggers at 27 µA current into the INV pin during abrupt load-dump events, forcing gate output low and entering idle state. Static OVP activates when the error amplifier saturates low under sustained light-load overvoltage, also disabling switching. Both modes reduce quiescent current to ≤2.2 mA to preserve Vcc hold-up time, as specified in Section 7.1 of the datasheet.

Can the L6562ATDTR operate without an auxiliary winding on the boost inductor?

Yes-the ZCD pin supports R-C network synchronization from the MOSFET drain, eliminating need for auxiliary winding. With R_ZCD = 330 kΩ and C_ZCD = 22–33 pF, the network transfers drain edges to ZCD for reliable zero-current detection, validated in 400 V output applications per Section 7.4 of the datasheet.

What is the functional difference between L6562ATDTR and L6562DTR?

L6562ATDTR adds digital leading-edge blanking on CS, relocates disable function to INV pin (vs. ZCD on L6562DTR), lowers dynamic OVP trigger from 40 µA to 27 µA, reduces CS clamp from 1.7 V to 1.08 V, and improves reference accuracy to 1% (vs. 2.4%). These changes require updated external components but deliver lower THD, reduced heat, and better energy-saving compliance.