STMicroelectronics L6562DTR

Overview

L6562DTR from STMicroelectronics is a transition-mode (TM) power factor correction (PFC) controller IC in SO-8 and DIP-8 packages, designed for AC-DC pre-regulators up to 300W. It features 1% internal reference voltage (2.5 V @ Tj = 25°C), ultra-low 70 µA start-up current, and a ±600/±800 mA totem-pole gate driver with UVLO pull-down and 12 V output clamp-enabling direct drive of high-current MOSFETs or IGBTs in IEC61000-3-2-compliant SMPS for desktop PCs, monitors, and AC adapters.

For engineers reviewing the L6562DTR datasheet, L6562DTR pinout, L6562DTR application, or L6562DTR equivalent, key selection criteria include its proprietary THD-optimized multiplier, dual-step overvoltage protection (static/dynamic), extended 10.3–22 V VCC operating range, and BCD process integration enabling low quiescent current (≤4 mA) and on-chip current-sense filtering.

Technical Context

The L6562DTR implements current-mode control in transition mode using a highly linear multiplier with built-in THD optimization circuitry that injects a controlled positive offset near line zero-crossings to minimize conduction dead-angle and reduce input current distortion across wide mains ranges (85–265 VAC). Its error amplifier uses a precise 2.5 V internal reference and supports external compensation between INV (pin 1) and COMP (pin 2) for stable voltage-loop regulation.

Zero-current detection (ZCD, pin 5) enables accurate demagnetization sensing for MOSFET turn-on timing, while the CS (pin 4) comparator compares sensed switch current against a sinusoidal reference derived from MULT (pin 3) to determine turn-off. The gate driver (GD, pin 7) delivers 600 mA source / 800 mA sink with clamped high-level output (~12 V) and UVLO-driven pull-down for safe MOSFET gate control.

Key Specifications

Pinout & Package

Available in ECOPACK®-compliant SO-8 and DIP-8 packages. SO-8 package dimensions: 4.9 mm × 6.0 mm × 1.75 mm (max height); DIP-8: 10.92 mm × 7.95 mm × 3.81 mm (max height). Both feature lead-free second-level interconnect per JEDEC JESD97.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar transition-mode PFC controller applications.

Compared with UCC28051DR and FAN7930C, the L6562DTR uniquely integrates THD optimization, dual-step OVP, and a robust ±800 mA gate driver in a single BCD-process IC-making it the only solution among the three capable of achieving <4% THD and <0.5 W no-load consumption in compact 80–300 W IEC61000-3-2-compliant designs without external protection or drive circuitry.

Availability

L6562DTR is available at Aetrix Electronics and suitable for desktop PC power supplies, LED TV adapters, and entry-level server PSUs requiring stable component supply, long-term lifecycle support, and ECOPACK®-compliant packaging.

Supply support for L6562DTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering innovative silicon solutions for automotive, industrial, and power applications with strong focus on energy efficiency and environmental compliance.

The L6562DTR belongs to ST's high-performance analog power IC portfolio, specifically engineered for cost-sensitive, high-reliability AC-DC PFC pre-regulators targeting IEC61000-3-2 compliance in consumer and computing power supplies.

FAQ

What is the purpose of the THD optimizer circuit in the L6562DTR?

The THD optimizer injects a controlled positive offset into the multiplier output near AC line zero-crossings to increase MOSFET conduction time when instantaneous line voltage is low. This minimizes conduction dead-angle caused by bridge rectifier residual voltage, reducing total harmonic distortion to as low as 3.6% at 85 VAC full load-verified on EVAL6562-80W demo board.

How does the dual-step overvoltage protection work?

The L6562DTR implements two independent OVP mechanisms: dynamic OVP triggers at 40 µA error amplifier output current during sudden load drops, forcing gate shutdown; static OVP activates when COMP saturates low under sustained no-load conditions, inducing burst-mode operation. Both reduce IC quiescent current to preserve VCC hold-up time.

Can the L6562DTR drive a 12 A MOSFET directly?

Yes-the ±800 mA gate driver (pin 7) provides sufficient peak current to charge/discharge typical 12 A MOSFET gates (e.g., STP12NM50, Qg ≈ 35 nC) within required switching times. Rise/fall times are 40–80 ns with 200 mA load, and output is clamped to ~12 V to prevent gate oxide overstress even with 22 V VCC.

What package options are available for the L6562DTR?

L6562DTR is supplied in tape-and-reel format for both SO-8 (4.9 × 6.0 mm body, 1.75 mm max height) and DIP-8 (10.92 × 7.95 mm body, 3.81 mm max height) packages. Both are ECOPACK®-certified with lead-free second-level interconnect per JEDEC JESD97 and marked accordingly on packaging.