STMicroelectronics L6563STR

Overview

L6563STR from STMicroelectronics is an enhanced transition-mode (TM) power factor correction (PFC) controller in SO14 package, designed for high-efficiency AC-DC pre-regulators. It features 1% internal voltage reference (@TJ = 25 °C), bidirectional 1/V² input voltage feedforward, tracking boost function, and a ±600/±800 mA totem-pole gate driver. It enables EN61000-3-2 and JEITA-MITI compliance in >400 W SMPS systems.

For engineers reviewing the L6563STR datasheet, L6563STR pinout, L6563STR application, or L6563STR equivalent, key selection considerations include its accurate OVP threshold (2.5 V on PFC_OK), latchable feedback failure protection, ZCD-based zero-current detection for TM operation, and remote ON/OFF control via RUN and PFC_OK pins.

Technical Context

The L6563STR implements current-mode control with a highly linear multiplier and proprietary 1/V² feedforward that dynamically adjusts loop gain during both line surges and drops-improving transient response without external compensation. Its tracking boost function uses TBO-pin–programmed current injection into INV to scale output voltage proportionally with RMS input voltage.

Protection architecture includes latched shutdown on feedback loop disconnection (INV < 1.66 V while PFC_OK > 2.5 V), inductor saturation detection via dual-threshold CS comparator (1.7 V fault level), and brownout handling via RUN pin threshold (0.8 V shutdown / 0.88 V restart). The GD output integrates active pull-down during UVLO.

Key Specifications

Pinout & Package

Package: SO14 (Small Outline, 14-lead, 150 mil width), compliant with JEDEC MS-012, thermal resistance R_thJA = 120 °C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PFC controller applications.

Compared with UCC28070DR and FAN6300MX, the L6563STR uniquely combines transition-mode operation, bidirectional line feedforward, and hardware-latched fault signaling-making it optimal for compact, standards-compliant, and safety-critical PFC stages up to 400 W.

Availability

L6563STR is available at Aetrix Electronics and suitable for server power supplies, industrial AC-DC modules, high-end desktop PC PSUs, and IEC61000-3-2 compliant adapters requiring stable component supply and long-term design-in support.

Supply support for L6563STR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, delivering automotive, industrial, and power management solutions with emphasis on reliability and energy efficiency.

The L6563STR belongs to ST's high-performance analog PFC controller product line, engineered specifically for transition-mode AC-DC front-ends demanding ultra-low THD, robust protection, and seamless interoperability with downstream DC-DC controllers.

FAQ

What is the purpose of the TBO pin on the L6563STR?

The TBO (Tracking Boost Output) pin provides a buffered version of the VFF voltage and sources a current proportional to the mains peak voltage. When connected to a resistor-to-ground, it sinks current from the INV pin to dynamically adjust the PFC output voltage in proportion to the input RMS voltage-reducing capacitor stress during brownout and improving efficiency at light loads.

How does the L6563STR handle feedback loop disconnection?

The L6563STR detects feedback loop disconnection by monitoring simultaneous conditions: PFC_OK voltage exceeding 2.5 V (indicating overvoltage) and INV voltage falling below 1.66 V (indicating open feedback). When both occur, it enters latched shutdown, asserts PWM_LATCH high, and requires Vcc cycling below 6 V to reset-ensuring fail-safe behavior in safety-critical systems.

Can the L6563STR drive a 600 V GaN HEMT directly?

No-the L6563STR's GD pin has a 12 V clamp and ±600/±800 mA drive strength optimized for silicon MOSFETs and IGBTs. Driving a 600 V GaN HEMT requires gate voltage levels, slew rate control, and negative turn-off capability beyond this IC's specification; a dedicated GaN gate driver (e.g., STGAP2S) must be used in cascade.

What is the minimum recommended value for the resistor on the VFF pin?

The datasheet specifies a minimum resistor value of 100 kΩ between VFF (pin 5) and ground. Using a lower resistance risks excessive current draw, degrading the internal peak-hold circuit accuracy and compromising 1/V² feedforward performance-leading to increased THD and unstable regulation under line transients.