Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > PFC (Power Factor Correction)

STMicroelectronics L6564TDTR

Name: L6564TDTR
Brand: STMicroelectronics
SKU: L6564TDTR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: L6564TDTR

Manufacturer:: STMicroelectronics

Category:: PFC (Power Factor Correction)

Package:: 10-SOP (0.154", 3.90mm Width)

Datasheet:: L6564TDTR.pdf

Description:: IC PFC CTRLR TRANSITION 10SSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:6,819

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

L6564TDTR from STMicroelectronics is a 10-pin transition-mode (TM) power factor correction (PFC) controller IC designed for high-efficiency AC-DC pre-regulators. It integrates a current-mode PWM controller, 1% internal voltage reference (@T_J = 25 °C), bi-directional 1/V² voltage feedforward, and a ±600/±800 mA totem-pole gate driver. It operates across -40 to 150 °C junction temperature and supports EN61000-3-2 and JEITA-MITI compliance in LED luminaires and server SMPS.

For engineers reviewing the L6564TDTR datasheet, L6564TDTR pinout, L6564TDTR application, or L6564TDTR equivalent, key selection criteria include its guaranteed outdoor temperature range (-40 to 150 °C), accurate adjustable overvoltage protection (2.5 V ±1.5%), latched feedback failure shutdown, inductor saturation detection (1.7 V threshold), and low 100 µA startup current - all critical for robust PFC design in high-reliability industrial and lighting systems.

Technical Context

The L6564TDTR implements fixed-off-time transition-mode control with a highly linear multiplier stage and proprietary 1/V² feedforward that dynamically compensates loop gain against RMS input voltage variation - enabling stable operation from 85–265 V_AC. Its zero-current detection (ZCD) input (Pin 7) triggers MOSFET turn-on at inductor demagnetization, ensuring quasi-resonant switching and low EMI.

Protection architecture includes three independent safety layers: (1) OVP latching at 2.5 V on PFC_OK (Pin 6), (2) feedback failure detection via simultaneous low INV (<1.66 V) and high PFC_OK (>2.5 V), and (3) inductor saturation detection via CS pin (Pin 4) comparator threshold at 1.7 V with automatic restart delay (150–700 µs). All operate without external components.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Operating Range	10.3–22.5 V: Supports wide-input auxiliary supplies; UVLO hysteresis of 2.7 V prevents chatter during brownout recovery.
Internal Reference Accuracy	1% @ T_J = 25 °C: Enables precise output voltage regulation (e.g., 385 V ±3.85 V) without trimming resistors.
Gate Driver Output	±600/±800 mA: Directly drives high-Q_g MOSFETs (e.g., STP16NF06L) without external buffers in ≤400 W designs.
Startup Current	≤180 µA: Allows use of high-value, cost-effective startup resistors (e.g., 1 MΩ from 300 V_DC) with fast wake-up.
OVP Threshold	2.5 V ±0.065 V: Sets PFC output overvoltage limit via resistor divider; latched shutdown prevents repeated fault cycling.
CS Pin Saturation Threshold	1.7 V ±0.1 V: Detects boost inductor saturation before core collapse, triggering safe converter halt and thermal stress reduction.
ZCD Trigger Voltage	Negative-going edge at 0.5–1.0 V: Ensures accurate zero-current switching timing across temperature (-40 to 150 °C).

Pinout & Package

SSOP10 package (3.9 mm × 4.9 mm, 0.65 mm pitch) with exposed pad for thermal enhancement; RoHS-compliant, moisture sensitivity level 3.

Pin/Terminal	Circuit Role	Design Meaning
1 (INV)	Inverting input of error amplifier	Receives scaled PFC output voltage; clamped at 8–9 V to prevent latch-up during transient overvoltage.
2 (COMP)	Error amplifier output	Drives multiplier input; burst-mode inhibition below 2.4 V prevents no-load runaway.
3 (MULT)	Main multiplier input	Accepts rectified mains via resistor divider (0–3 V range); enables sinusoidal current shaping.
4 (CS)	Current sense input	Detects MOSFET current; 1.7 V threshold triggers immediate shutdown on inductor saturation.
5 (VFF)	Voltage feedforward input	Derives RMS line voltage via internal peak-hold; enables 1/V² correction and bidirectional line transient response.
6 (PFC_OK)	OVP / disable / fault monitor	2.5 V OVP latch, 0.23 V remote shutdown, and feedback failure detection (with INV) - all on single pin.
7 (ZCD)	Zero-current detector input	Senses boost diode reverse recovery; negative edge triggers MOSFET turn-on for TM operation.
8 (GND)	Signal and power ground	Common return for analog circuitry and gate driver; requires low-inductance layout to avoid noise coupling.
9 (GD)	Gate driver output	Totem-pole stage clamped at 12 V; drives gate capacitance directly with 600 mA source / 800 mA sink capability.
10 (V_CC)	Supply input	Self-limited to 28 V Zener; powers both analog core and gate driver; bypass capacitor (0.1 µF) recommended.

Key Features

Feature	Design Value
Bi-directional 1/V² feedforward	Compensates loop gain against RMS input voltage variation - improves THD <5% across 85–265 V_AC and 20–100% load.
Latched feedback failure protection	Detects open/shorted optocoupler or divider fault by correlating low INV (<1.66 V) and high PFC_OK (>2.5 V); requires V_CC cycle to reset.
Inductor saturation detection	Hardware-based CS pin comparator (1.7 V threshold) halts switching within 350 ns to prevent MOSFET avalanche stress.
Low-power idle states	Quiescent current drops to 1.5–2.5 µA when PFC_OK < 0.23 V or during OVP latch - extends hold-up time in standby.
AC brownout detection	VFF pin monitors line drop via internal comparator (0.8 V shutdown / 0.88 V restart); eliminates need for external undervoltage IC.

Applications

LED Street Lighting Driver

Server PSU PFC Stage

Use Scenario: Outdoor LED luminaire operating from 90–305 V_AC with >5-year field life requirement.

IC Role / Device Role / Timing Role: Primary PFC controller enforcing EN61000-3-2 Class C limits; regulates 400 V_DC bus with 1% reference stability.

Use Value: Guaranteed -40 to 150 °C operation avoids derating; 100 µA startup enables direct HV startup without auxiliary winding.

Use Scenario: 80 PLUS Titanium 1.5 kW server PSU requiring >98% PFC efficiency at 50% load.

IC Role / Device Role / Timing Role: Transition-mode PFC controller managing boost stage; uses ZCD (Pin 7) for precise zero-current turn-on timing.

Use Value: ±800 mA sink capability drives 30 nC gate charge MOSFETs directly; 1/V² feedforward maintains THD <3% during 115 V_AC brownout.

IEC61000-3-2 Compliant Adapter

Industrial Motor Drive Pre-regulator

Use Scenario: 100 W desktop adapter certified to IEC61000-3-2 with universal input (100–240 V_AC).

IC Role / Device Role / Timing Role: PFC controller implementing fixed-off-time TM control; uses MULT (Pin 3) and VFF (Pin 5) for harmonic cancellation.

Use Value: Integrated THD optimizer circuit reduces 3rd harmonic distortion by 40% vs. standard TM controllers - passes Class D limits at full load.

Use Scenario: 3-phase VFD with active front-end requiring robust PFC under unbalanced grid conditions.

IC Role / Device Role / Timing Role: Standalone PFC controller monitoring DC bus via PFC_OK (Pin 6); disables output during overvoltage events.

Use Value: Latched OVP (2.5 V threshold) prevents repeated fault cycling during regenerative braking surges; GND-referenced GD (Pin 9) simplifies gate drive isolation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar PFC controller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ICE3PCS01G	Fixed-frequency CCM controller; no ZCD input; requires external OVP comparator.	Targets higher-power (>500 W) continuous conduction mode designs; lacks TM-specific protections.	Select when CCM operation and higher power density outweigh need for TM EMI advantages.
UCC28056	8-pin TM controller; no integrated 1/V² feedforward; relies on external resistor network for line compensation.	Optimized for cost-sensitive consumer adapters; lacks latched feedback failure protection.	Select for <100 W applications where simplified BOM offsets missing fault coverage.

Compared with ICE3PCS01G and UCC28056, the L6564TDTR uniquely combines transition-mode operation, hardware-enforced latched fault protection, and monolithic 1/V² feedforward - delivering superior THD performance and reliability in outdoor-rated and industrial PFC stages without external compensation.

Availability

L6564TDTR is available at Aetrix Electronics and suitable for LED street lighting drivers, server PSU PFC stages, IEC61000-3-2 compliant adapters, and industrial motor drive pre-regulators requiring stable component supply across extended temperature and long product lifecycles.

Supply support for L6564TDTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, analog, and microcontroller solutions for industrial, automotive, and energy-efficient applications.

The L6564TDTR belongs to ST's high-reliability PFC controller product line, engineered specifically for outdoor-rated and mission-critical AC-DC conversion where thermal resilience, fault robustness, and regulatory compliance are non-negotiable.

FAQ

What is the purpose of the VFF pin (Pin 5) and how must it be configured?

The VFF pin implements ST's proprietary 1/V² voltage feedforward for line-voltage-dependent loop gain compensation. It must be connected to GND via a resistor (100 kΩ to 2 MΩ) and capacitor (1 µF typical) to complete the internal peak-hold circuit. Direct grounding violates the datasheet and disables brownout detection, which triggers at 0.8 V on this pin.

How does the L6564TDTR detect and respond to boost inductor saturation?

It monitors the CS pin (Pin 4) with a dedicated comparator set to 1.7 V. When sensed current exceeds this threshold - indicating core saturation - the IC immediately halts switching, enters a safe idle state (quiescent current ~2 µA), and waits 150–700 µs before attempting restart. This prevents MOSFET avalanche failure without software intervention.

Can the PFC_OK pin (Pin 6) be used for both overvoltage protection and remote on/off control?

Yes - it serves three functions: (1) OVP latch at 2.5 V (rising edge), (2) remote shutdown at 0.23 V (falling edge), and (3) feedback failure detection when combined with INV < 1.66 V. The thresholds are internally trimmed and temperature-compensated; no external components are required for any function.

What is the maximum allowable voltage on the GD pin (Pin 9) and why is clamping important?

The GD pin output is clamped to 12 V (typical) during high-side drive to prevent MOSFET gate oxide overstress. This internal clamp eliminates need for external Zener diodes in gate drive circuits. The clamp activates only during sourcing; sinking capability remains unclamped at 0.6–1.4 V low-level output for clean turn-off.

L6564TDTR Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 10-SOP (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Mode:: Discontinuous (Transition)

Frequency - Switching:: -

Current - Startup:: 90 µA

Voltage - Supply:: 10.3V ~ 22.5V

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 10-SSOP

L6564TDTR FAQ

1.How can I place an order for L6564TDTR through Aetrix?

Please submit a Request for Quotation (RFQ) for L6564TDTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for L6564TDTR reliable?

The price and inventory of L6564TDTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L6564TDTR is usually 5 days.

3.What payment methods are accepted for L6564TDTR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L6564TDTR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for L6564TDTR?

L6564TDTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your L6564TDTR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for L6564TDTR?

For technical support, including L6564TDTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L6564TDTR requirements.

6.How does Aetrix verify that L6564TDTR is sourced from the original manufacturer or authorized distributors?

All L6564TDTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L6564TDTR meets industry standards.

7.What is the process for return or replacement of L6564TDTR?

All L6564TDTR units undergo pre-shipment inspection (PSI). If there is an issue with L6564TDTR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The L6564TDTR part is unused and in its original packaging.

Return procedure for L6564TDTR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…