STMicroelectronics L6566A
- Part No.:
- L6566A
- Manufacturer:
- STMicroelectronics
- Category:
- AC DC Converters, Offline Switches
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
L6566A.pdf
- Description:
- IC OFFLINE SWITCH FLYBACK 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:962
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Product details
Overview
L6566A from STMicroelectronics is a multi-mode current-mode PWM controller IC designed for high-performance offline flyback converters with PFC front-end stages. It supports selectable fixed-frequency (FF) or quasi-resonant (QR) operation, features 700 V high-voltage startup, adaptive UVLO, line feedforward for constant power regulation, and dual-level OCP with transformer saturation detection. It targets >150 W AC-DC power supplies in LCD TVs and notebook adapters.
For engineers reviewing the L6566A datasheet, L6566A pinout, L6566A application, or L6566A equivalent, key selection considerations include its QR/FF mode flexibility, 800 mA totem-pole gate driver, programmable soft-start, brownout protection threshold (0.45 V), and PFC interface capability via Vcc_PFC output.
Technical Context
The L6566A integrates a programmable oscillator (1 V reference + external R-to-GND) that sets switching frequency in FF mode or maximum frequency in QR mode. Its ZCD input enables valley-switching detection for zero-voltage turn-on, while MODE/SC pin configures operation mode and provides slope compensation ramp in FF mode.
It implements advanced protection logic: pulse-by-pulse OCP at CS pin with 0.450 V/0.485 V thresholds, latched or auto-restart OVP via ZCD (5 V trip), brownout shutdown at AC_OK < 0.45 V, and hiccup-mode overload response timed by SS capacitor discharge. The adaptive UVLO adjusts turn-off threshold dynamically to counter self-supply droop under light load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Modes | Fixed-frequency (FF) or quasi-resonant (QR); selected via MODE/SC pin connection to VREF |
| Startup Voltage | 700 V HV startup on HVS pin; internal 1 mA current source charges Vcc until UVLO turn-on threshold |
| Gate Drive | ±800 mA totem-pole output with active pull-down during UVLO; drives MOSFET/IGBT directly |
| OCP Thresholds | Primary OCP at CS: 0.450 V (pulse-by-pulse), secondary saturation OCP at 1.5 V (latched) |
| VFF Input Range | 0–3 V linear feedforward range; scales current limit inversely with mains voltage for constant power |
| Quiescent Current | <3 mA typical; enables compliance with energy-saving standards at no-load and light-load conditions |
| Brownout Threshold | AC_OK pin trips at <0.45 V (with 15 µA hysteresis); disables IC, clears latches, and opens Vcc_PFC |
Pinout & Package
Package: SO16N (16-pin small outline, 150 mil width, JEDEC MS-012AC).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| HVS (Pin 1) | High-voltage startup input | Withstands 700 V; internally sources 1 mA to charge Vcc capacitor until UVLO turn-on |
| GND (Pin 3) | Signal and power ground return | Common return for gate drive, bias, and sensing; requires dedicated low-noise PCB track |
| GD (Pin 4) | Gate driver output | ±800 mA totem-pole stage; actively pulls down during UVLO to prevent shoot-through |
| Vcc (Pin 5) | Main supply rail | Powered by HV startup or auxiliary winding; UVLO turn-on ~14 V, turn-off ~8.5 V (adaptive) |
| Vcc_PFC (Pin 6) | PFC controller supply output | Switched rail enabled at startup; disabled when COMP < threshold or during fault/latch |
| CS (Pin 7) | Current sense input | Accepts MOSFET current-sense voltage; 150 ns blanking, dual-threshold OCP (0.450 V / 1.5 V) |
| DIS (Pin 8) | Latched disable input | ≥4.5 V triggers latch-off; cleared only by Vcc falling below UVLO - requires power recycle |
| COMP (Pin 9) | Error amplifier output | 2.5–5 V control range; < threshold initiates burst-mode; bottom-clamped at ~2 V |
| VREF (Pin 10) | Internal 5 V reference | ±2% accuracy; supplies external circuitry (≤ few mA); monitored for fault latching |
| ZCD (Pin 11) | Zero-current detection / OVP input | Negative edge triggers QR turn-on; ≥5 V causes OVP shutdown (latch/auto-restart selectable) |
| MODE/SC (Pin 12) | Mode select / slope compensation | Tied to VREF → QR mode; floating → FF mode; outputs ramp for slope comp in FF |
| OSC (Pin 13) | Oscillator programming | 1 V reference; external R-to-GND sets frequency (FF) or max freq (QR) |
| SS (Pin 14) | Soft-start timing | Internal current charges external capacitor; controls duty ramp-up and OLP delay timing |
| VFF (Pin 15) | Line voltage feedforward | 0–3 V input scales OCP threshold inversely with mains voltage for constant power |
| AC_OK (Pin 16) | Brownout monitor | <0.45 V disables IC, clears latches, opens Vcc_PFC; hysteresis via 15 µA current source |
Key Features
| Feature | Design Value |
|---|---|
| Multi-mode topology support | Single IC supports both fixed-frequency and quasi-resonant flyback topologies via pin-strapping |
| Integrated PFC interface | Vcc_PFC pin delivers switched 12–15 V supply to PFC controller and disables it at light load |
| Adaptive undervoltage lockout | UVLO turn-off threshold lowers under light load to maintain stable Vcc despite transformer parasitics |
| Dual-level overcurrent protection | Primary pulse-by-pulse OCP (0.450 V) + secondary saturation OCP (1.5 V) with independent latching |
| Controlled burst-mode operation | Automatically engages at very light load using COMP pin voltage; reduces standby power to <3 mA |
| Transformer saturation detection | CS pin monitors for abnormal current rise; 1.5 V threshold triggers latched shutdown to prevent core damage |
Applications
| LCD TV Power Supply | Notebook Adapter |
|---|---|
|
Use Scenario: 190–240 VAC input, 12–24 VDC output, >150 W continuous power with EN61000-3-2 compliance. IC Role / Device Role / Timing Role: Primary-side QR flyback controller managing MOSFET gate drive, ZCD-based valley switching, and PFC coordination via Vcc_PFC. Use Value: Enables >90% efficiency at full load and <300 mW no-load consumption via adaptive UVLO and burst-mode. |
Use Scenario: Universal-input (90–264 VAC), 19 V/4.74 A output, compact adapter with thermal and surge robustness. IC Role / Device Role / Timing Role: Fixed-frequency current-mode controller with line feedforward (VFF) and leading-edge blanking for noise immunity in high-density layout. Use Value: Maintains constant output power across input range and survives 300 VAC surges via 700 V HVS pin. |
| PDP TV Auxiliary Supply | Set-Top Box Power Module |
|
Use Scenario: Standby-sensitive auxiliary rail (5 V/2 A) powering logic and display circuits in plasma display panels. IC Role / Device Role / Timing Role: Burst-mode controller with COMP-driven light-load management and brownout recovery (AC_OK) for grid instability resilience. Use Value: Achieves <150 mW standby power and recovers automatically after brief brownouts without full reset. |
Use Scenario: Dual-output (12 V + 3.3 V), 35 W consumer-grade power module meeting ENERGY STAR Tier 2 requirements. IC Role / Device Role / Timing Role: Multi-mode controller enabling QR operation at full load and FF at medium load for optimal EMI/efficiency trade-off. Use Value: Reduces audible noise via valley skipping and meets conducted EMI limits without oversized filters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-mode flyback controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC28064A | TI part with integrated 600 V startup, no Vcc_PFC output; uses different OVP architecture (ZCD-based but non-strobed) | Lacks dedicated PFC interface; requires external regulator for PFC IC supply; less suitable for two-stage systems requiring coordinated light-load shutdown | Select when PFC integration is not required and TI ecosystem preference exists; verify ZCD noise immunity in high-dV/dt environments |
| ICE2QS03G | Infineon quasi-resonant controller with integrated 650 V startup; no FF mode; lacks line feedforward and adaptive UVLO | Fixed QR-only operation; cannot implement constant-power feedforward; less flexible for universal-input designs with wide VAC range | Choose for cost-sensitive QR-only applications where input voltage variation is limited and PFC coordination is handled externally |
Compared with UCC28064A and ICE2QS03G, the L6566A uniquely combines FF/QR dual-mode operation, integrated PFC supply control (Vcc_PFC), line feedforward (VFF), and adaptive UVLO - making it optimal for high-efficiency, two-stage, wide-input AC-DC systems requiring regulatory compliance and low standby loss.
Availability
L6566A is available at Aetrix Electronics and suitable for LCD TV power supplies, notebook adapters, and set-top box power modules requiring stable component supply, long-term lifecycle assurance, and full production traceability.
Supply support for L6566A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, analog, MCU, and automotive ICs with vertical manufacturing and broad industrial qualification.
The L6566A belongs to ST's high-voltage AC-DC controller product line, engineered specifically for energy-efficient, two-stage offline SMPS targeting EN61000-3-2 compliance and sub-300 mW no-load consumption.
FAQ
What is the function of the Vcc_PFC pin and how is it controlled?
The Vcc_PFC pin (Pin 6) delivers a regulated 12–15 V supply to an external PFC controller IC. It is internally connected to Vcc via a controlled switch that closes at startup and opens when the COMP pin voltage drops below a threshold (indicating light load), during latch faults, or during UVLO. This enables coordinated PFC shutdown to reduce system standby power.
How does the adaptive UVLO improve reliability in flyback converters?
The adaptive UVLO dynamically lowers the Vcc turn-off threshold under light load to compensate for reduced self-supply voltage caused by transformer leakage inductance and winding resistance. This prevents unintended shutdown during burst-mode operation while maintaining robust start-up at full load - ensuring stable operation across the entire load range.
Can the L6566A operate in quasi-resonant mode without an auxiliary winding?
No. Quasi-resonant operation requires the ZCD pin (Pin 11) to be connected to the transformer's auxiliary winding via a resistor divider to detect demagnetization zero-crossing. Without this signal, the IC defaults to fixed-frequency mode regardless of MODE/SC pin configuration - the ZCD input is mandatory for QR triggering.
What determines whether OVP at the ZCD pin operates in latched or auto-restart mode?
OVP latching behavior at ZCD is determined by external resistor configuration per Table 7 in the datasheet: connecting a resistor between ZCD and VREF selects auto-restart; leaving ZCD open or tying it directly to VREF selects latched shutdown. The internal digital filter and strobing ensure noise immunity independent of mode selection.
L6566A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Output Isolation:
- Isolated
- Internal Switch(s):
- No
- Voltage - Breakdown:
- -
- Topology:
- Flyback
- Voltage - Start Up:
- 14 V
- Voltage - Supply (Vcc/Vdd):
- 8V ~ 23V
- Duty Cycle:
- 70%
- Frequency - Switching:
- 100kHz
- Power (Watts):
- -
- Fault Protection:
- Current Limiting, Over Load
- Control Features:
- Frequency Control, Soft Start
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 16-SO
- Mounting Type:
- Surface Mount
L6566A FAQ
1.How can I place an order for L6566A through Aetrix?
Please submit a Request for Quotation (RFQ) for L6566A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for L6566A reliable?
The price and inventory of L6566A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L6566A is usually 5 days.
3.What payment methods are accepted for L6566A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L6566A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for L6566A?
L6566A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your L6566A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for L6566A?
For technical support, including L6566A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L6566A requirements.
6.How does Aetrix verify that L6566A is sourced from the original manufacturer or authorized distributors?
All L6566A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L6566A meets industry standards.
7.What is the process for return or replacement of L6566A?
All L6566A units undergo pre-shipment inspection (PSI). If there is an issue with L6566A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The L6566A part is unused and in its original packaging.
Return procedure for L6566A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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