STMicroelectronics L6599AFD

Overview

L6599AFD from STMicroelectronics is a very low temperature–improved high-voltage resonant controller IC for series-resonant half-bridge topologies, delivering 50% complementary duty cycle, up to 65.8 kHz operating frequency, 600 V rail-compatible high-side gate driver with integrated synchronous bootstrap diode, and two-level overcurrent protection (frequency-shift + latched shutdown). It is deployed in outdoor LED drivers requiring operation down to –50 °C.

For engineers reviewing the L6599AFD datasheet, L6599AFD pinout, L6599AFD application, or L6599AFD equivalent, key selection concerns include resonant frequency modulation range, –50 °C guaranteed operation, dual OCP response timing, bootstrap diode integration, and PFC interface compatibility in AC-DC adapter designs.

Technical Context

The L6599AFD implements a relaxation oscillator with externally programmable minimum frequency (via RFmin pin's 2 V reference and R-C network) and variable-frequency control via feedback-modulated charging current into CF pin. Its fixed 0.2–0.4 µs deadtime ensures soft-switching across load conditions.

It integrates dual-level protection: first-level OCP triggers non-linear frequency shift (via Css discharge) upon ISEN > 0.8 V, while second-level latching occurs at ISEN > 1.5 V; DIS input provides independent latched shutdown, and LINE input enables brownout detection with 13 µA hysteresis current.

Key Specifications

Pinout & Package

Package: SO16N (16-pin small outline, narrow body, 1.27 mm pitch), RoHS-compliant, rated for T_j = –50 to +150 °C.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar resonant half-bridge controller applications.

Compared with UCC256301 and ICE2PCS01, the L6599AFD uniquely delivers –50 °C operation, integrated synchronous bootstrap, and standalone high-voltage half-bridge control-making it irreplaceable for ruggedized outdoor LED and industrial SMPS where thermal margin and BOM simplicity are critical.

Availability

L6599AFD is available at Aetrix Electronics and suitable for outdoor LED drivers, street lighting systems, and AC-DC open-frame SMPS requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for L6599AFD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing analog, MCU, power, and automotive ICs with strong focus on industrial and energy-efficient applications.

The L6599AFD belongs to ST's high-voltage resonant controller product line, engineered specifically for robust, high-efficiency LLC and series-resonant half-bridge power supplies operating in harsh thermal and electrical environments.

FAQ

What is the purpose of the DELAY pin (Pin 2) and how does it affect OCP behavior?

The DELAY pin implements a programmable time-delayed OCP response: when ISEN exceeds 0.8 V, an internal 150 µA current charges the external capacitor on this pin. At 2 V, the controller forces maximum frequency to limit power; at 3.5 V, it latches off. The external R-C network sets both delay duration and restart hysteresis (restart at <0.3 V), enabling controlled intermittent operation under short-circuit conditions without immediate shutdown.

Can the L6599AFD drive 600 V GaN FETs directly, and what are the voltage limits on HVG and VBOOT?

Yes-the L6599AFD's high-side driver is rated for 600 V rail compatibility: VBOOT withstands –1 to +618 V, and HVG operates within VOUT –0.3 V to VBOOT +0.3 V. Its 0.3 A source / 0.7 A sink capability and <60 ns rise time meet gate-drive requirements for most 600 V GaN HEMTs, provided layout minimizes parasitic inductance and OUT node ringing is suppressed per layout guidelines in Section 7.1 of the datasheet.

How does the PFC_STOP function interact with burst mode and fault conditions?

PFC_STOP is an open-drain output that pulls low during four conditions: DIS > 1.85 V (latched shutdown), ISEN > 1.5 V (OCP latch), LINE > 6 V (overvoltage), or STBY < 1.24 V (burst mode entry). It remains low during DELAY > 2 V and releases only when DELAY falls below 0.3 V or UVLO occurs. This allows coordinated PFC disable during all major fault and low-power states without additional logic.

Is the RFmin pin (Pin 4) only for setting minimum frequency, or does it serve additional functions?

Pin 4 serves three confirmed roles: (1) provides a 2 V ±3% reference for setting f_min via RFmin resistor to GND; (2) accepts feedback current from optocoupler collector to modulate oscillator frequency for regulation; and (3) accepts R-C network for soft-start frequency ramp shaping. All three functions are electrically verified in Sections 4.2, 6.1, and 6.3 of the datasheet and share the same pin with no multiplexing.