STMicroelectronics L6599ATDTR

Overview

L6599ATDTR from STMicroelectronics is a high-voltage resonant half-bridge controller IC designed for series-resonant LLC and LCC topologies. It delivers 50% complementary duty cycle, 600 V rail-compatible high-side gate drive with integrated synchronous bootstrap diode, two-level overcurrent protection (frequency shift + latched shutdown), and burst-mode operation at light load - enabling >94% efficiency in AC-DC SMPS for LCD TVs and telecom power supplies.

For engineers reviewing the L6599ATDTR datasheet, L6599ATDTR pinout, L6599ATDTR application, or L6599ATDTR equivalent, key selection criteria include its 500 kHz max operating frequency, -300/700 mA dual gate drivers with UVLO pull-down, non-linear soft-start for monotonic V_OUT rise, and PFC interface capability for coordinated pre-regulator control.

Technical Context

The L6599ATDTR implements a relaxation oscillator with externally programmable minimum frequency (via RFmin pin's 2 V reference and current-sourcing network) and variable-frequency regulation via optocoupler feedback into the same node. Its fixed 0.2–0.4 µs deadtime ensures ZVS across the resonant tank, while internal leading-edge blanking (250 ns) rejects switching noise on the ISEN input.

It integrates dual independent gate drivers: a 600 V-rated high-side driver (HVG/OUT/VBOOT) with synchronous bootstrap diode (R_DS(on) = 150 Ω) and dv/dt immunity up to 50 V/ns, plus a low-side driver (LVG/GND) with -300/700 mA peak sourcing/sinking and active UVLO pull-down - both referenced to separate grounds for robust half-bridge operation.

Key Specifications

Pinout & Package

Package: SO16N (16-pin small outline, 150 mil width, ECOPACK® compliant).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-voltage resonant half-bridge controller applications.

Compared with UCC256301 and IR3584M, the L6599ATDTR provides analog simplicity, integrated 600 V drivers with synchronous bootstrap, and native PFC coordination - making it optimal for cost-sensitive, high-reliability AC-DC resonant converters where digital overhead is unnecessary.

Availability

L6599ATDTR is available at Aetrix Electronics and suitable for LCD TV power supplies, telecom SMPS, and industrial open-frame converters requiring stable component supply with guaranteed long-term manufacturability and automotive-grade qualification support.

Supply support for L6599ATDTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and power applications since 1987.

The L6599ATDTR belongs to ST's high-voltage resonant controller product line, engineered specifically for zero-voltage-switching (ZVS) half-bridge topologies in energy-efficient AC-DC conversion - targeting compliance with ENERGY STAR®, DoE Level VI, and EU CoC Tier 2 standards.

FAQ

What is the purpose of the DELAY pin (Pin 2) and how is it configured?

The DELAY pin implements a programmable overcurrent timeout using an external RC network. When ISEN exceeds 0.8 V, a 150 µA current charges the capacitor; reaching 2 V forces maximum frequency, and exceeding 3.5 V triggers latched shutdown. Discharge via the resistor sets restart delay. Typical values: 100 nF capacitor + 100 kΩ resistor yield ~15 ms hold-off before latch.

Can the L6599ATDTR drive GaN HEMTs directly, and what are the layout constraints?

Yes - its -300/700 mA gate drivers and <60 ns rise/fall times support common 10–20 nC GaN FETs. Critical layout requirements include: (1) separate GND and OUT copper pours with minimal loop area; (2) VBOOT capacitor placed <2 mm from Pins 14/16; (3) guard ring around Pin 13 (NC) to maintain creepage between HV and LV sections per IEC 62368.

How does the PFC_STOP function interact with burst mode operation?

During burst mode (STBY < 1.24 V), the PFC_STOP pin is actively pulled low, disabling the PFC controller to eliminate pre-regulator losses. This occurs simultaneously with half-bridge gate drive suspension. The pin returns high-Z when STBY rises above 1.29 V, allowing PFC restart before resonant stage resumption - ensuring coordinated sequencing without output droop.

Is the RFmin pin (Pin 4) compatible with standard optocoupler feedback configurations?

Yes - Pin 4 accepts standard TL431-based optocoupler circuits. The 2 V reference and ±3% accuracy allow direct connection of the phototransistor collector through a series resistor. For 60 kHz–300 kHz range, typical R_Fmin = 12 kΩ (sets f_min) and R_Fmax = 2.7 kΩ (sets f_max), with C_F = 470 pF. No additional compensation is needed for stable loop response.