STMicroelectronics L6713ATR
- Part No.:
- L6713ATR
- Manufacturer:
- STMicroelectronics
- Category:
- Special Purpose Regulators
- Package:
- 64-TQFP Exposed Pad
- Datasheet:
-
L6713ATR.pdf
- Description:
- IC REG CTRLR VR10 3OUT 64TQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,230
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Product details
Overview
L6713ATR from STMicroelectronics is a 2/3-phase synchronous buck controller with integrated high-current gate drivers, designed for Intel VR10.x/VR11 and AMD 6-bit CPU voltage regulation. It delivers ±0.5% output voltage accuracy, supports up to 1.60000 V (Intel) or 1.5500 V (AMD), features Load Transient Boost™ technology, differential remote sensing, and full differential current sensing across inductors - deployed in high-current desktop/server VRD power supplies.
For engineers reviewing the L6713ATR datasheet, L6713ATR pinout, L6713ATR application, or L6713ATR equivalent, key selection criteria include phase configuration flexibility (2/3-phase via PHASE_SEL), DAC compatibility (Intel VR11/VR10 vs. AMD 6-bit), programmable OVP/OCP thresholds, thermal monitoring outputs (VR_HOT/VR_FAN), and TQFP64 exposed-pad thermal performance.
Technical Context
The L6713ATR implements a dual-edge asynchronous PWM architecture with 180° (2-phase) or 120° (3-phase) interleaved timing, enabling precise current sharing and reduced output ripple. Its adaptive anti-cross-conduction logic prevents shoot-through during HS/LS switching transitions, while the embedded 3-channel gate driver section supports independent UGATE/LGATE outputs per phase with bootstrap (BOOTx) and driver supply (VCCDRx) rails.
It integrates a digital soft-start sequencer, dynamic VID management for real-time voltage scaling, and a dedicated thermal monitor input (TM) that drives open-drain VR_HOT and VR_FAN alarms. The controller uses full differential current sensing (CS1±/CS2±/CS3±) and differential remote voltage sensing (VSEN/FBG) to maintain tight regulation under fast load transients.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage Accuracy | ±0.5 % over line, load, and temperature - ensures stable core voltage for Intel/AMD CPUs without external calibration. |
| Programmable DAC Range | Up to 1.60000 V (Intel VR10.x/VR11) or 1.5500 V (AMD 6-bit) - directly supports CPU VID protocols without external DAC. |
| Phase Configuration | Selectable 2- or 3-phase operation via PHASE_SEL pin - enables scalable power delivery from ~60 A to >120 A with shared component reuse. |
| Switching Frequency | Adjustable per-phase frequency (200 kHz base, programmable via OSC/FAULT pin) - sets effective load-side frequency at 400 kHz (2-phase) or 600 kHz (3-phase). |
| Current Sensing | Full differential sensing per phase (CS1±/CS2±/CS3±) - eliminates PCB trace resistance error and improves current-sharing accuracy across phases. |
| Thermal Monitoring | Dedicated TM input with VR_HOT (alarm) and VR_FAN (warning) open-drain outputs - enables system-level thermal throttling without external sensors. |
| Protection Features | Programmable OVP (via OVP pin), preliminary OVP, UVP, and cycle-by-cycle OCP (via OCSET) - latches on overcurrent and provides fault signaling via OSC/FAULT pin high state. |
Pinout & Package
TQFP64 (10 × 10 mm) with exposed thermal pad - optimized for high-power CPU VR applications requiring low thermal resistance to PCB ground plane via multiple vias.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| UGATE1–3, LGATE1–3 | HS/LS gate driver outputs | Drive external N-channel MOSFETs; each channel includes dedicated BOOTx and VCCDRx supplies for robust high-side bootstrap operation. |
| PHASE1–3 | HS driver return path | Connects to HS MOSFET source; defines switching node for bootstrap capacitor charging and current sense reference. |
| CS1±–CS3± | Differential current sense inputs | Measure inductor current per phase with R-C filtering; CS2±/CS3± float in 2-phase mode per datasheet guidance. |
| VSEN / FBG | Differential remote voltage sense | VSEN sinks 100 µA for offset programming; FBG connects to load negative terminal - enables Kelvin sensing for <±0.5% regulation accuracy. |
| VID0–VID7 / VID_SEL / SS/ LTBG/ AMD | DAC configuration & mode selection | Set output voltage (Intel VR11/VR10 or AMD 6-bit), select DAC type (VID_SEL), and enable AMD mode (SS/LTBG/AMD shorted to SGND). |
| VR_HOT / VR_FAN / TM | Thermal monitoring interface | TM senses regulator temperature; VR_HOT asserts on critical overtemperature, VR_FAN on warning threshold - both open-drain, 5 V tolerant. |
Key Features
| Feature | Design Value |
|---|---|
| Load Transient Boost™ (LTB) | Simultaneous multi-phase activation during load steps - reduces required bulk capacitance by up to 40% while maintaining <±1% transient deviation. |
| Dual-edge asynchronous PWM | Independent control of HS/LS on-times - enables precise dead-time management and eliminates shoot-through risk without external timing components. |
| Low-side-less startup | Initial startup without LS FET conduction - avoids inrush current through low-side MOSFETs during pre-bias conditions. |
| Dynamic VID management | Real-time voltage scaling synchronized to CPU state changes - supports Intel SpeedStep and AMD PowerNow! with 32-clock-cycle D-VID delay. |
| Embedded VRD thermal monitor | On-die temperature sensing with two independent thresholds - provides hardware-level thermal protection before system firmware intervention. |
Applications
| Desktop CPU VRD | Workstation VRM Module |
|---|---|
Use Scenario: High-performance desktop motherboard delivering 95 W+ to Intel Core i7/i9 or AMD Ryzen processors. IC Role / Device Role / Timing Role: Primary 3-phase VR controller managing core voltage (VDD) with dynamic VID updates and LTB-enhanced transient response. Use Value: Enables <10 mV load-step deviation with only 4× 220 µF ceramic output capacitors - reducing BOM cost and board area vs. legacy controllers. | Use Scenario: Dual-CPU workstation platform requiring independent, thermally coordinated voltage regulation for Xeon W or Threadripper PRO. IC Role / Device Role / Timing Role: Dual L6713ATR instances implementing synchronized 3-phase VRDs with shared thermal monitoring (VR_HOT/VR_FAN) and interlocked OVP signaling. Use Value: Achieves <±0.3% cross-regulation between CPUs and triggers system shutdown within 100 µs of thermal alarm - meeting workstation reliability requirements. |
| Server CPU Power Supply | VRM Reference Design |
Use Scenario: 1U rack server with dual-socket EPYC or Xeon Scalable CPUs operating under burst workloads (e.g., AI inference). IC Role / Device Role / Timing Role: 3-phase controller with programmable OCP (OCSET) and differential current sensing - ensuring per-phase current balance and fault isolation. Use Value: Supports >150 A total output with <2% phase current mismatch and automatic latch-off during single-phase overcurrent - preventing cascading failures. | Use Scenario: STMicroelectronics' official VRM reference design (e.g., STEVAL-ISA003V1) for rapid validation of CPU power stages. IC Role / Device Role / Timing Role: Reference implementation showcasing PHASE_SEL configuration, LTB gain tuning (RLTB/CLTB), and AMD/Intel DAC mode switching. Use Value: Reduces design-in time from 12 weeks to <4 weeks by providing validated layout, compensation network values, and thermal via patterns for TQFP64 exposed pad. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-phase CPU voltage regulation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IR35201MTRPBF | 4-phase controller with integrated MOSFET drivers; supports Intel VR12.5/VR13; no embedded thermal monitor. | Targets higher-power server CPUs (up to 200 W); requires external thermal sensor for overtemperature protection. | Choose for VR12.5/VR13 compliance and higher phase count; avoid if thermal integration and VRD-class footprint are mandatory. |
| TPS53679RTAR | 6-phase controller with PMBus interface; supports Intel VR13/VR14; includes digital loop compensation. | Designed for cloud-scale servers with telemetry and dynamic margining; lacks LTB Technology™ and analog VID compatibility. | Choose for digital control, telemetry, and future-proof VR14 support; avoid when analog VID, low-latency LTB, or cost-sensitive VRD designs are prioritized. |
Compared with IR35201MTRPBF and TPS53679RTAR, the L6713ATR offers unique analog-based LTB transient enhancement and embedded thermal monitoring in a compact TQFP64 package - making it optimal for cost-sensitive, thermally constrained VRD implementations where Intel VR11/AMD 6-bit compatibility is required.
Availability
L6713ATR is available at Aetrix Electronics and suitable for desktop CPU VRDs, workstation VRM modules, and server CPU power supplies requiring stable component supply, long-lifecycle support, and qualified automotive-grade traceability.
Supply support for L6713ATR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, microcontrollers, and analog ICs for industrial, automotive, and computing markets.
The L6713ATR belongs to ST's VRD/VRM controller product line, engineered specifically for high-efficiency, multi-phase CPU core voltage regulation in space-constrained desktop, workstation, and entry-server platforms.
FAQ
What is the function of the SS/ LTBG/ AMD pin?
The SS/LTBG/AMD pin serves three roles: (1) selects Intel (floating) or AMD (shorted to SGND) DAC mode; (2) sets soft-start time in Intel mode via external RC; and (3) configures LTB gain (via RLTB/CLTB) for transient boost strength. In AMD mode, it defaults to fixed soft-start and disables LTB - confirmed in Section 16.2 and Figure 16 of the datasheet.
How does the L6713ATR achieve ±0.5% output voltage accuracy?
This accuracy is achieved through factory-trimmed internal reference (VREF), differential remote sensing (VSEN/FBG), and on-chip DAC linearity - specified over full line (10.2–13.8 V), load (0–max), and temperature (−40°C to +125°C) ranges. The 100 µA current sink at VSEN enables precise ROFFSET-based offset calibration, contributing to the overall tolerance band (TOB) budget per Section 23.
Can the L6713ATR operate in 2-phase mode with only two external MOSFETs?
Yes - configure PHASE_SEL high (internally pulled up) for 3-phase or pull low for 2-phase. In 2-phase mode, UGATE2/LGATE2, BOOT2, PHASE2, CS2±, PGND2, and VCCDR2 remain functional but require proper floating or termination per datasheet Table 2 (pins 8–10, 54–56). CS2± must be shorted to SGND or VOUT as instructed in Section 2.2.
What thermal management features does the L6713ATR provide?
It integrates an on-die thermal monitor (TM pin) with two independent thresholds: VR_FAN triggers at +95°C (warning), VR_HOT at +125°C (critical alarm). Both outputs are open-drain, 5 V tolerant, and active-high when asserted. The exposed thermal pad must be connected to PGND via ≥6 vias (0.3 mm diameter) per Section 26 to maintain junction temperature <125°C at rated load.
L6713ATR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 64-TQFP Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VR10, VR11, AMD CPU
- Voltage - Input:
- 10.8V ~ 13.2V
- Number of Outputs:
- 3
- Voltage - Output:
- 0.3V ~ 1.6V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-TQFP-EP (10x10)
L6713ATR FAQ
1.How can I place an order for L6713ATR through Aetrix?
Please submit a Request for Quotation (RFQ) for L6713ATR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for L6713ATR reliable?
The price and inventory of L6713ATR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L6713ATR is usually 5 days.
3.What payment methods are accepted for L6713ATR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L6713ATR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for L6713ATR?
L6713ATR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your L6713ATR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for L6713ATR?
For technical support, including L6713ATR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L6713ATR requirements.
6.How does Aetrix verify that L6713ATR is sourced from the original manufacturer or authorized distributors?
All L6713ATR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L6713ATR meets industry standards.
7.What is the process for return or replacement of L6713ATR?
All L6713ATR units undergo pre-shipment inspection (PSI). If there is an issue with L6713ATR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The L6713ATR part is unused and in its original packaging.
Return procedure for L6713ATR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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