STMicroelectronics L6728HTR

Overview

L6728HTR from STMicroelectronics is a single-phase synchronous buck PWM controller with integrated high-current gate drivers, 0.8 V internal reference, ±0.8 % output voltage accuracy, fixed 300 kHz switching frequency, and sensorless over-current protection via low-side R_DS(on) sensing. It operates from 5–12 V supply and supports input voltages as low as 1.5 V, targeting CPU/DSP core power supplies requiring precise regulation and fast transient response.

For engineers reviewing the L6728HTR datasheet, L6728HTR pinout, L6728HTR application, or L6728HTR equivalent, this controller delivers verified voltage-mode control loop performance (15 MHz GBWP, 8 V/µs slew rate), programmable dual-level OCP, PGOOD monitoring, and pre-bias start-up management in a compact DFN10 package - critical for memory, MCH/IOCH, and distributed DC-DC subsystem designs.

Technical Context

L6728HTR implements a voltage-mode error amplifier with 120 dB DC gain and 15 MHz gain-bandwidth product to support high-loop bandwidth for fast load-step response. Its adaptive anti-cross-conduction logic uses PHASE and LGATE pin sensing to dynamically adjust dead time, minimizing body-diode conduction without external Schottky diodes.

The device embeds dual-level over-current protection: a user-programmable first threshold (50–550 mV via ROCSET resistor) and an internal second threshold at 1.5× that value. OVP/UVP and VSEN disconnection protection are implemented using dedicated comparators referenced to the 0.8 V internal bandgap, with PGOOD assertion tied to VSEN window compliance after soft-start completion.

Key Specifications

Pinout & Package

Package: DFN10 (3 mm × 3 mm, 0.5 mm pitch, exposed thermal pad). Compact footprint supports high-density power delivery in space-constrained applications such as server DIMMs and embedded controllers.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck controller applications.

Compared with ISL6269CRZ-T and TPS54620RGYR, L6728HTR uniquely combines LSLess start-up, sensorless dual-level OCP, and DFN10 integration for high-reliability, pre-biased POL applications where discrete FET optimization and thermal headroom are prioritized over monolithic simplicity.

Availability

L6728HTR is available at Aetrix Electronics and suitable for CPU core power, memory termination, MCH/IOCH subsystems, and distributed DC-DC converters requiring stable component supply, long-lifecycle support, and traceable sourcing for industrial and embedded OEM programs.

Supply support for L6728HTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs, with broad manufacturing scale and automotive-grade quality systems.

L6728HTR belongs to ST's high-performance DC-DC controller product line, designed specifically for efficient, reliable, and compact synchronous buck conversion in computing, networking, and industrial embedded power systems.

FAQ

What is the minimum input voltage supported by L6728HTR?

L6728HTR supports power conversion input as low as 1.5 V, enabled by its flexible gate drive architecture and internal bootstrap circuitry. This allows use with low-voltage intermediate buses or battery-backed rails, provided the VCC supply remains within its 5–12 V operating range and duty cycle constraints are observed.

How is over-current protection configured without a sense resistor?

OCP is configured by connecting a resistor (ROCSET) between LGATE and GND. During startup, an internal 10 µA current flows through ROCSET, generating a voltage sampled as the first-level OCP threshold (50–550 mV). The second level is automatically set to 1.5× that value, enabling dual-level protection using only the LS MOSFET's R_DS(on).

Does L6728HTR support pre-biased output start-up?

Yes - L6728HTR implements LSLess (Low-Side-Less) start-up. During soft-start, the LS driver remains disabled until the HS begins switching, preventing reverse current flow and negative voltage spikes when the output is pre-biased. If HS fails to switch (e.g., due to high pre-bias), LS is enabled at soft-start timeout to discharge the output.

What thermal considerations apply to the DFN10 package?

The DFN10 package has R_th(JC) = 5 °C/W and R_th(JA) = 45 °C/W (on 2s2p board). To maintain T_J ≤ 125 °C, the exposed thermal pad must be soldered to ≥2 cm² of inner-layer copper pour with ≥4 thermal vias. Power dissipation includes bias (~6 mA × VCC) plus gate-drive losses dependent on MOSFET Q_g and FSW.