STMicroelectronics L6732TR

Overview

L6732TR from STMicroelectronics is an adjustable synchronous step-down DC-DC controller IC designed for high-current, high-efficiency buck converters. It supports input voltage from 1.8 V to 14 V, supplies regulated output down to 0.6 V with ±0.8 % accuracy over −40 °C to +125 °C, and delivers up to 20 A output current using external N-channel MOSFETs in a synchronous rectified topology.

For engineers reviewing the L6732TR datasheet, L6732TR pinout, L6732TR application, or L6732TR equivalent, key selection considerations include its predictive anti-cross-conduction control, programmable R_DS(on)-based over-current protection (OCP) on both high-side and low-side FETs, 250/500 kHz selectable switching frequency, pre-bias startup capability, and master/slave synchronization with 180° phase shift for multi-phase designs.

Technical Context

The L6732TR implements fixed-frequency voltage-mode PWM control with a 10 MHz gain-bandwidth error amplifier and 5 V/µs slew rate, enabling fast transient response in high-density DC-DC modules. Its oscillator supports dual-frequency selection (250 kHz or 500 kHz) via analog voltage at the EAREF pin, and minimum on-time is guaranteed below 100 ns for low-duty-cycle operation at high frequencies.

Current sensing uses R_DS(on) of external MOSFETs-peak current sensed via OCH pin (high-side), valley current via OCL pin (low-side)-eliminating sense resistors. The device integrates high-current gate drivers (R_{HGATE_ON} = 1.7 Ω, R_{LGATE_OFF} = 0.6 Ω), predictive dead-time control (~20 ns adaptive dead time), and internal 5 V LDO (VCCDR) with bypass option for low-V_CC operation.

Key Specifications

Pinout & Package

Package: HTSSOP16 with exposed thermal pad - optimized for high-power density and thermal dissipation in compact DC-DC modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck controller applications.

Compared with ISL6269CRZ-T and TPS54620RGYT, the L6732TR offers unique advantages for high-current, high-accuracy, and multi-phase applications: external reference support enables voltage tracking, dual R_DS(on) OCP improves reliability under transient faults, and master/slave sync enables scalable multi-phase architectures without external clocking.

Availability

L6732TR is available at Aetrix Electronics and suitable for LCD/PDP TV power supplies, high-density DC-DC modules, and DDR memory regulation requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for L6732TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and automotive ICs with emphasis on energy efficiency and system integration.

The L6732TR belongs to ST's high-performance DC-DC controller product line, engineered specifically for synchronous buck topologies in computing, graphics, and telecom infrastructure where precision, scalability, and thermal efficiency are critical.

FAQ

What is the minimum output voltage supported by the L6732TR?

The L6732TR supports an adjustable output voltage down to 0.6 V with ±0.8 % accuracy over temperature (−40 °C to +125 °C) and line regulation. This is achieved using either the internal 0.6 V reference or an external reference applied to the EAREF pin, enabling precise regulation for modern low-voltage ASICs and memory interfaces.

Does the L6732TR support pre-biased output startup?

Yes - the L6732TR supports pre-biased startup by sourcing current only during the soft-start ramp (SS pin voltage 0–1.1 V). This prevents reverse current flow and ensures controlled ramp-up even when the output is initially charged, making it ideal for DDR memory and FPGA core supplies where output pre-bias is common.

How does the L6732TR implement over-current protection without sense resistors?

The L6732TR uses R_DS(on) of the external high-side and low-side MOSFETs for current sensing. Peak current is monitored via the OCH pin (100 µA sink current through ROCH), and valley current via the OCL pin (100 µA source current through ROCL), eliminating sense resistors while maintaining accuracy across temperature and load conditions.

Can multiple L6732TR controllers be synchronized for interleaved operation?

Yes - the L6732TR supports master/slave synchronization via the SYNCH pin, enabling two or more devices to operate with 180° phase shift. When SYNCH pins are tied together, the highest-frequency device becomes master; all others automatically align with 180° offset, reducing input/output ripple and improving thermal distribution.