STMicroelectronics L6756D
- Part No.:
- L6756D
- Manufacturer:
- STMicroelectronics
- Category:
- Special Purpose Regulators
- Package:
- 40-VFQFN Exposed Pad
- Datasheet:
-
L6756D.pdf
- Description:
- IC REG CTRLR VR10 4OUT 40VFQFPN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
L6756D from STMicroelectronics is a 2/3/4-phase buck controller for Intel VR10, VR11, and VR11.1 CPU power delivery, featuring LTB Technology® for ultra-fast load transient response, ±0.5% output voltage accuracy over line/load/temperature, and full-differential DCR current sensing. It supports programmable oscillator (100 kHz–1 MHz), PSI#-managed low-power states, and remote sense with feedback disconnection protection - deployed in high-current VRM/VRD for server CPUs and GPU power rails.
For engineers reviewing the L6756D datasheet, L6756D pinout, L6756D application, or L6756D equivalent, key selection criteria include phase scalability (2–4), VR10/VR11.x DAC compatibility (7/8-bit VID), dual-edge asynchronous architecture, LTB gain control, and VFQFPN40 6×6 mm thermal performance with RthJC = 1 °C/W.
Technical Context
The L6756D implements a dual-edge asynchronous PWM architecture with per-phase current sensing via CSx/CSxN inputs and integrated droop-based current sharing. Its LTB Technology® dynamically adjusts loop gain using the LTB and LTB_GAIN pins to minimize output voltage deviation during rapid load steps.
It embeds a 7/8-bit programmable DAC supporting Intel VR10 (6-bit VID + offset) and VR11.1 (8-bit VID) protocols, with VSEN/FBG remote sensing, adjustable soft-start (via SS pin), and PSI#-triggered low-power state entry. The device uses differential current sensing across DCR and provides Imon output for real-time load monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Phase Support | Configurable 2-, 3-, or 4-phase operation via G2/G4 pin strapping - enables scalable current delivery up to >200 A with external drivers. |
| Output Voltage Accuracy | ±0.5% over line, load, and temperature - ensures stable core voltage under dynamic CPU workloads without recalibration. |
| VID Resolution | 7-bit (VR10) / 8-bit (VR11.1) - supports 6.25 mV LSB steps down to 0.05 V, enabling fine-grained voltage positioning for power/performance tuning. |
| Oscillator Range | 100 kHz to 1 MHz (per phase) - higher frequency reduces output filter size; total effective switching frequency scales linearly with phase count (e.g., 400 kHz at 4-phase). |
| Current Sensing | Full-differential DCR sensing with dedicated CSx/CSxN inputs - rejects common-mode noise and enables accurate per-phase current readback. |
| Protection Features | OVP/UVP (150–200 mV / −400 mV thresholds), FB disconnection detection (550–750 mV), and ILIM-based overcurrent shutdown - prevents damage during miswiring or fault conditions. |
| Package | VFQFPN40 6×6 mm with exposed thermal pad - achieves RthJC = 1 °C/W for high-power density CPU VRMs on compact PCB layouts. |
Pinout & Package
VFQFPN40 6×6 mm package with 40-pin layout and exposed thermal pad connected to PGND plane for optimal thermal dissipation (RthJC = 1 °C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 EN | Enable input | Internally pulled-up 10 μA to 3.3 V; pull-low disables controller - supports sequenced power-up and system-level enable control. |
| 2–9 VID0–VID7 | VR11.1 voltage ID inputs | 3.3 V-tolerant digital inputs defining output voltage per Intel spec; support dynamic DVID transitions with ±0.5% accuracy. |
| 10 PSI#/VR10 | Power-state indicator / DAC mode select | Configured by PSI_A pin: asserts low for VR11 low-power state entry or selects VR10/VR11 DAC mapping when shorted to SGND. |
| 11 SS | Soft-start timing | Resistor-to-GND sets TSS with 18.52 μs/kΩ gain - enables LSLESS startup over pre-biased outputs to avoid reverse inductor current. |
| 12 ROSC | Oscillator frequency set | Resistor-to-GND programs FSW (10 kHz/μA); floating = 200 kHz per phase - determines ripple, efficiency, and filter component sizing. |
| 13 ILIM | Overcurrent threshold | Sources DROOP current; OC triggers at 1.7 V - sets per-phase current limit independent of DCR tolerance and temperature drift. |
| 17 VSEN / 16 FBG | Remote sense inputs | VSEN sinks 50 μA for positive offset; FBG referenced to load ground - enables Kelvin sensing to compensate PCB IR drop. |
| 21–28 CS1N–CS4 | Differential current sense | Per-phase DCR sensing inputs with R-C filtering - supports accurate current sharing and fast OCP response across all active phases. |
| 30–33 G1–G4 | PWM gate drive outputs | CMOS outputs driving external high-side MOSFET drivers; floating = HiZ - allows phase shedding and seamless transition between 2/3/4-phase modes. |
| 40 IMON | Current monitor output | Sources current proportional to total load current; clamped to 1.1 V max - provides analog load indicator compatible with VR11.1 CPU monitoring. |
Key Features
| Feature | Design Value |
|---|---|
| LTB Technology® | Dynamic loop gain adjustment via LTB/LTB_GAIN pins minimizes voltage deviation during >10 A/μs load transients - reduces required bulk capacitance by up to 40%. |
| LSLESS Startup | Soft-start initiates from VBOOT (1.081 V typ) instead of 0 V - eliminates negative current spikes and inductor saturation when powering pre-biased rails. |
| Flexible Driver Interface | DRVON CMOS output controls external driver HiZ state; Gx outputs float to disable phases - enables adaptive phase shedding and lossless light-load operation. |
| Feedback Disconnection Protection | Detects open-sense connections via VFB-DISC (550–750 mV threshold) and FBG-DISC (400–600 mV) - disables regulation before damaging load ICs. |
| VR_RDY Open-Drain Status | Asserts low only during faults (OVP/UVP/OC); floats after soft-start - provides clean power-good signal for CPU reset sequencing and system management. |
Applications
| Server CPU VRM | Workstation GPU Power |
|---|---|
Use Scenario: High-current, multi-phase core voltage regulation for dual-socket Xeon Scalable processors with dynamic DVID transitions. IC Role / Device Role / Timing Role: Primary multiphase buck controller managing up to 4 phases, VID decoding, current sharing, and PSI#-driven C-state entry/exit. Use Value: ±0.5% voltage accuracy maintains CPU stability during turbo boost; LTB Technology® limits ΔVOUT to <15 mV during 50 A/μs load steps. |
Use Scenario: Compact, high-density 3-phase VRM for NVIDIA A100 or AMD Radeon Pro GPUs requiring tight voltage positioning and thermal headroom. IC Role / Device Role / Timing Role: Phase-scalable controller with remote sense, differential DCR current monitoring, and programmable soft-start for safe GPU rail ramp-up. Use Value: VFQFPN40 package enables <8 mm² footprint; full-differential sensing rejects board noise, improving current readback accuracy to ±4%. |
| Desktop High-End CPU VRD | AI Accelerator Board Power |
Use Scenario: VRD-compliant 2-phase solution for Intel Core i9/K-series CPUs with aggressive transient requirements and legacy VR10 compatibility. IC Role / Device Role / Timing Role: Dual-phase controller configured via G2 strapping, supporting VR10 DAC mode (PSI_A shorted to SGND) and 6-bit VID decoding. Use Value: 0.5% accuracy and LSLESS startup ensure reliable cold boot and resume-from-suspend; IMON output feeds system telemetry for power optimization. |
Use Scenario: Modular 4-phase power stage for FPGA-based AI inference accelerators requiring programmable voltage offsets and precise current reporting. IC Role / Device Role / Timing Role: Controller with VDRP pin for voltage positioning implementation and IMON output scaled for FPGA ADC input - enables closed-loop load-line tuning. Use Value: Adjustable oscillator (100 kHz–1 MHz) allows trade-off between efficiency (low fSW) and transient response (high fSW) per application profile. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multiphase buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6367IRZ | 6-phase capable, integrated MOSFET drivers, no LTB Technology®, 0.3% voltage accuracy | Targets higher-current server platforms (>300 A); lacks VR11.1 DAC support and PSI#-managed low-power states | Select for higher phase count and driver integration; not suitable for VR11.1 DVID or low-power state management. |
| TPS53679RTAR | 4-phase, integrated drivers, D-CAP3 control, 0.5% accuracy, supports VR12.0/VR13 | Designed for newer Intel/AMD CPUs with adaptive voltage positioning; no VR10 backward compatibility or LTB gain tuning | Choose for VR12+/adaptive control; requires redesign for VR10/VR11.1 systems and loses LTB's transient edge. |
Compared with ISL6367IRZ and TPS53679RTAR, the L6756D uniquely balances VR10/VR11.1 backward compatibility, LTB-enhanced transient response, and discrete driver flexibility - making it optimal for cost-sensitive, thermally constrained VRM designs where phase scalability and legacy support are critical.
Availability
L6756D is available at Aetrix Electronics and suitable for server CPU VRMs, workstation GPU power supplies, and high-end desktop VRDs requiring stable component supply, long-term lifecycle support, and traceable sourcing for industrial deployment.
Supply support for L6756D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs, with deep expertise in CPU/GPU power delivery solutions.
The L6756D belongs to ST's VRM/VRD controller product line, designed specifically for Intel-compatible high-current, low-voltage CPU and GPU power applications with emphasis on transient response, accuracy, and thermal efficiency.
FAQ
What is the purpose of the LTB and LTB_GAIN pins?
The LTB pin accepts an external signal to dynamically adjust loop gain during load transients, while LTB_GAIN sets the sensitivity of this boost action. Together they implement ST's Load Transient Boost Technology® - reducing output voltage deviation by up to 60% during rapid load steps without increasing output capacitance.
How does LSLESS startup prevent reverse current flow?
LSLESS (Low-Side-Less) startup begins regulation from VBOOT (1.081 V typical) rather than 0 V, eliminating the need for low-side MOSFET conduction during initial ramp-up. This avoids reverse current through the inductor and prevents negative voltage spikes at the load, critical for powering pre-biased rails safely.
Can the L6756D operate in 2-phase mode with VR11.1 DAC support?
Yes - configure G2 and G4 pins to GND for 2-phase operation while maintaining full VR11.1 8-bit VID support. The controller retains all features including DVID transitions, LTB, remote sensing, and IMON output, with identical ±0.5% voltage accuracy and current sharing capability.
What is the function of the VR_RDY pin and how should it be used?
VR_RDY is an open-drain status output that floats after soft-start completion and pulls low only during active protection events (OVP, UVP, OC). It must be pulled up to ≤3.3 V; it provides a clean, fault-aware power-good signal for CPU reset sequencing and system management controllers without requiring external logic.
L6756D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 40-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- Controller, Intel VR10, VR11, VR11.1
- Voltage - Input:
- 10.8V ~ 13.2V
- Number of Outputs:
- 4
- Voltage - Output:
- 0.3V ~ 1.6V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-VFQFPN (6x6)
L6756D FAQ
1.How can I place an order for L6756D through Aetrix?
Please submit a Request for Quotation (RFQ) for L6756D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for L6756D reliable?
The price and inventory of L6756D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L6756D is usually 5 days.
3.What payment methods are accepted for L6756D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L6756D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for L6756D?
L6756D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your L6756D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for L6756D?
For technical support, including L6756D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L6756D requirements.
6.How does Aetrix verify that L6756D is sourced from the original manufacturer or authorized distributors?
All L6756D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L6756D meets industry standards.
7.What is the process for return or replacement of L6756D?
All L6756D units undergo pre-shipment inspection (PSI). If there is an issue with L6756D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The L6756D part is unused and in its original packaging.
Return procedure for L6756D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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