STMicroelectronics L6758A
- Part No.:
- L6758A
- Manufacturer:
- STMicroelectronics
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
L6758A.pdf
- Description:
- IC REG CTRLR VR12 2OUT 48VFQFPN
- Quantity:
- Payment:

- Shipping:

Inventory:2,576
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
L6758A from STMicroelectronics is a VR12-compliant dual-phase controller IC for high-current CPU voltage regulation, supporting (4+1)-phase topology with 25 MHz SVID bus v1.5, 0.5% output voltage accuracy, and dual independent oscillators (200 kHz base, adjustable up to 550 kHz). It powers Intel® VR12 processors in desktop/server/workstation platforms requiring adaptive voltage positioning and dynamic phase management.
For engineers reviewing the L6758A datasheet, L6758A pinout, L6758A application, or L6758A equivalent, key selection criteria include VR12 SVID compliance, dual-section thermal compensation via single NTC, per-phase current sensing with DCR-based differential monitoring, and VFDE/GDC-driven efficiency optimization across load transients.
Technical Context
The L6758A implements two independent control loops: a multi-phase (2–4 phase) core section with second-generation LTB Technology™ for fast transient response and a dedicated single-phase GFX/VSA section. Both sections support fully-differential current sensing across DCR, AVP, and pre-biased startup.
It integrates VR12 serial VID bus management with programmable IMAX/TMAX/VBOOT/ADDRESS registers, dual remote sense inputs (RGND/VSEN and SRGND/SVSEN), and dual fault managers delivering average + per-phase overcurrent protection, OV/UV, and FB disconnection detection - all synchronized via shared thermal monitor logic using TM/ST pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VR12 Compliance | Fully compliant with Intel VR12 spec, including 25 MHz SVID bus v1.5 for dynamic VID programming of IMAX, TMAX, VBOOT, and address. |
| Output Voltage Accuracy | ±0.5% over temperature and line/load, enabling tight regulation for modern CPU cores requiring precise AVP implementation. |
| Phase Configuration | Multi-phase section supports 2–4 phases for core; single-phase section for graphics/system agent - both independently configurable via pinstrapping. |
| Oscillator Range | Multi-phase OSC: 180–220 kHz (base), adjustable to 450–550 kHz; Single-phase SOSC: 207–253 kHz (base), adjustable to 493–667 kHz. |
| Current Sensing | Fully-differential DCR-based sensing per phase (CS1P/N through CS4P/N) plus single-phase SCSP/SNSN; IMON/SIMON outputs provide proportional current monitoring. |
| Thermal Compensation | Single NTC design supports simultaneous thermal compensation for both sections via TM/ST pins with programmable TCOMP/STCOMP gain resistors. |
| Protection Features | Dual OC (average + per-phase), OV (+175 mV), UV, FB disconnection, and dual VR_RDY signaling - all latched with independent fault management. |
Pinout & Package
Package: VFQFPN48, 6 × 6 mm, 0.4 mm pitch, exposed thermal pad (GND).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 LTB | Multi-phase LTB input | Enables second-generation LTB Technology™ for optimized loop compensation and transient response in multi-phase section. |
| 2 IMON | Multi-phase current monitor output | Sources current proportional to total core load; 1.55 V threshold triggers latched OC protection. |
| 3 RGND / 19 SRGND | Remote ground sense | Connects to negative side of respective load to eliminate PCB IR drop error in voltage regulation. |
| 4 VSEN / 20 SVSEN | Remote output voltage sense | Sinks fixed 50 µA; used for OV/UV protection and closed-loop regulation in core and GFX sections. |
| 5 FB / 21 SFB | Error amplifier inverting input | Connected to VSEN via RFB; forms feedback node for multi-phase/single-phase regulation loops. |
| 6 COMP/DPM / 22 SCOMP/TMAX | Error amplifier output | Drives compensation network; RDPM/RTMAX resistor sets DPM strategy or TMAX register value. |
| 36–39 PWM1–PWM4 | Multi-phase gate drive outputs | CMOS PWM signals with HiZ capability; pinstrapped (e.g., pull-up on PWM4) to configure active phase count (2–4). |
| 14 SPWM/SEN | Single-phase gate drive output | Drives external driver; HiZ status managed internally; disable by connecting to VCC5 via 1 kΩ. |
| 34 ENDRV / 35 SENDRV | Driver enable outputs | CMOS enables for multi-phase and single-phase external drivers; synchronized with PWM HiZ windows for efficiency. |
| 32 OSC / 25 SOSC | Oscillator programming pins | Resistor-to-GND sets switching frequency: 10 kHz/µA gain; floating = 200 kHz (multi-phase) or 230 kHz (single-phase). |
| 26 IMAX/SIMAX | Current limit programming | Resistor divider between GND/VCC5 sets IMAX register for both sections - critical for OC threshold calibration. |
| 27 BOOT/ADDR | Boot voltage & SVID address | Resistor divider configures VBOOT and SVI bus address - required for proper VR12 communication handshake. |
| 15 VR_HOT / 40 SVR_RDY | Thermal alarm & ready signals | Open-drain outputs: VR_HOT asserts low when TM/ST exceeds TMAX; SVR_RDY releases after single-phase soft-start. |
Key Features
| Feature | Design Value |
|---|---|
| Second-generation LTB Technology™ | Reduces output filter component count by optimizing transient response without sacrificing stability - validated in multi-phase core regulation. |
| VFDE + GDC efficiency optimization | Variable Frequency Diode Emulation and Gate Drive Control dynamically adjust switching behavior to minimize conduction and switching losses at light loads. |
| Dual independent oscillator control | Separate OSC and SOSC pins allow distinct frequency tuning for core (2–4 phase) and GFX/VSA (1-phase) sections - essential for load-matching efficiency. |
| Pre-biased output management | Supports startup into pre-charged output rails without reverse current flow - required for hot-plug and multi-rail sequencing in server VRMs. |
| Dual remote sense + AVP | Simultaneous RGND/VSEN and SRGND/SVSEN inputs enable precise adaptive voltage positioning with load-line slope compensation per section. |
Applications
| Desktop CPU VRM | Server Core Regulator |
|---|---|
|
Use Scenario: High-performance desktop motherboard powering Intel Core i7/i9 processors with dynamic power states. IC Role / Device Role / Timing Role: Dual-section VR12 controller managing 4-phase core and 1-phase system agent under SVID command. Use Value: Enables <1% voltage deviation during 50 A/µs load steps while maintaining 90%+ efficiency at 50% load via DPM and VFDE. |
Use Scenario: Dual-socket server board with Xeon Scalable CPUs requiring redundant, thermally compensated voltage regulation. IC Role / Device Role / Timing Role: Primary VR controller implementing dual remote sense, per-phase OC, and VR_HOT thermal alarm for system-level thermal management. Use Value: Single NTC network (TM/ST) reduces BOM cost by 33% vs. dual-sensor solutions while delivering accurate load-line thermal compensation for both sections. |
| Workstation GFX Power | VSA Power Delivery |
|
Use Scenario: Professional workstation GPU power delivery where transient response must match GPU clock scaling. IC Role / Device Role / Timing Role: Dedicated single-phase section (SPWM/SEN) regulating GPU memory or compute rail with independent oscillator and current sense. Use Value: Independent SOSC tuning allows 300 kHz operation for faster transient recovery than core section - reducing GPU voltage droop during shader bursts. |
Use Scenario: System Agent (VSA) power rail in high-core-count CPUs where leakage dominates idle power. IC Role / Device Role / Timing Role: Single-phase section configured for low-quiescent, high-efficiency operation using GDC and DPM to disable phases during C-states. Use Value: GDC-controlled gate drive timing cuts switching losses by 22% at 10% load, extending battery life in mobile workstations and reducing heat in fanless enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar VR12 dual-controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6367 | Single-package dual controller with integrated MOSFET drivers; lacks separate SOSC/OSC pins - fixed 300 kHz base frequency for both sections. | Targeted at cost-sensitive client platforms; no independent thermal compensation for GFX section - uses shared NTC only. | Select ISL6367 only if driver integration eliminates need for external DrMOS and thermal requirements are less stringent. |
| TPS53679 | TI's VR12.5/VR13 controller with PMBus interface; supports 6-phase core + 2-phase GFX; includes internal DACs and telemetry reporting not present in L6758A. | Designed for next-gen servers with firmware-upgradable VRMs; requires PMBus host controller instead of SVID-only microcontroller. | Choose TPS53679 when telemetry, firmware updates, or >4-phase core scalability are mandatory - not for VR12-only legacy designs. |
Compared with ISL6367 and TPS53679, the L6758A uniquely balances VR12 compliance, independent dual-oscillator tuning, and single-NTC thermal compensation - making it optimal for high-density server/desktop VRMs where phase-specific efficiency and thermal margin are prioritized over telemetry or driver integration.
Availability
L6758A is available at Aetrix Electronics and suitable for desktop motherboards, server VRMs, workstation GPU power systems, and Intel VSA power delivery requiring stable component supply and long-term lifecycle support.
Supply support for L6758A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, microcontrollers, and analog ICs for industrial, automotive, and computing markets.
The L6758A belongs to ST's VR12 dual-controller product line, engineered specifically for high-current, multi-phase CPU voltage regulation in Intel platform-compliant systems - emphasizing transient performance, thermal robustness, and SVID interoperability.
FAQ
What is the function of the LTB pin (Pin 1) on the L6758A?
The LTB pin connects to the LTB Technology™ compensation network for the multi-phase section. It accepts an external RC network that shapes the error amplifier response to optimize transient performance and stability without requiring complex loop tuning. This pin is not used in the single-phase section and must be connected per Section 11.2 of the datasheet to achieve specified load-step response.
How does the L6758A implement adaptive voltage positioning (AVP)?
The L6758A implements AVP through its dual-section load-line architecture: the COMP and SCOMP pins generate voltage droop proportional to sensed current (IMON/SIMON), while REF and SREF provide offset-adjusted references. External resistors (RREF, RSREF) set the load-line slope, and thermal compensation via TM/ST further adjusts droop based on temperature - all without host processor intervention.
Can the L6758A operate with only two active phases in the multi-phase section?
Yes - the L6758A supports 2-, 3-, or 4-phase operation in the multi-phase section via pinstrapping: pulling PWM4 high configures 3-phase mode; pulling both PWM3 and PWM4 high configures 2-phase mode. Unused current sense pins (e.g., CS3P/N, CS4P/N) must be shorted to the regulated output voltage as specified in Table 2, Pin Description.
What is the role of the GDC pin (Pin 8) and how is it used?
The GDC (Gate Drive Control) pin enables dynamic adjustment of gate drive timing to reduce switching losses at light loads. When enabled, it modulates the dead-time and slew rate of PWM outputs based on load current. If unused, GDC may be left floating; no pull-up/down is required. Its effect is validated in efficiency curves at 10–20% load in the datasheet's Figure 23.
L6758A Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VR12
- Voltage - Input:
- 10.8V ~ 13.2V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.25V ~ 1.52V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VFQFPN (6x6)
L6758A FAQ
1.How can I place an order for L6758A through Aetrix?
Please submit a Request for Quotation (RFQ) for L6758A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for L6758A reliable?
The price and inventory of L6758A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L6758A is usually 5 days.
3.What payment methods are accepted for L6758A?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L6758A transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for L6758A?
L6758A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your L6758A order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for L6758A?
For technical support, including L6758A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L6758A requirements.
6.How does Aetrix verify that L6758A is sourced from the original manufacturer or authorized distributors?
All L6758A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L6758A meets industry standards.
7.What is the process for return or replacement of L6758A?
All L6758A units undergo pre-shipment inspection (PSI). If there is an issue with L6758A, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The L6758A part is unused and in its original packaging.
Return procedure for L6758A:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
L6758A Tags

-
TPS51206DSQR
Texas Instruments

-
TPS51200DRCR
Texas Instruments

-
TPS51200DRCT
Texas Instruments

-
TPS62740DSSR
Texas Instruments

-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi

-
RT9026GSP
Richtek USA Inc.

-
LP2998MRX/NOPB
Texas Instruments

-
TPS51200QDRCRQ1
Texas Instruments

-
DPA423GN-TL
Power Integrations

-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

