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STMicroelectronics L6759D
- Part No.:
- L6759D
- Manufacturer:
- STMicroelectronics
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
L6759D.pdf
- Description:
- IC REG CTRLR VR12 2OUT 48VFQFPN
- Quantity:
- Payment:
- Shipping:
Inventory:2,289
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Product details
Overview
L6759D from STMicroelectronics is a VR12-compliant dual-phase controller IC for DDR3 memory power delivery in server platforms, featuring 3-phase VDDQ and independent 1-phase VTT regulation, 25 MHz SVID bus compliance (Rev 1.5), 0.5% output voltage accuracy, and full-differential DCR current sensing.
For engineers reviewing the L6759D datasheet, L6759D pinout, L6759D application, or L6759D equivalent, this device supports dynamic phase management (DPM), adaptive voltage positioning (AVP), VFDE gate drive control, dual remote sense, and PMBus programmability for Intel VR12 memory rail sequencing and thermal compensation.
Technical Context
The L6759D implements two independent control loops: a 3-phase multi-phase section for VDDQ with per-phase current monitoring, load-line droop, and average/peak OC protection; and a dedicated 1-phase section for VTT that tracks VDDQ at half-scale with independent oscillator (SOSC) and current-sense circuitry.
It integrates second-generation LTB Technology™ for fast transient response, JMode for voltage positioning configuration, single-NTC thermal monitoring (TM/TCOMP) for VR_HOT assertion and load-line compensation, and dual error amplifiers with differential feedback (VSEN/SVSEN, FB/SFB) supporting AVP and pre-biased startup.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VR12 Compliance | Fully compliant with Intel VR12 spec, including 25 MHz SVID Rev 1.5 with programmable IMAX, TMAX, VBOOT, and ADDRESS. |
| Output Configuration | 3+1 dual-output: 3-phase for VDDQ (DDR3 core supply), 1-phase for VTT (termination supply), with VTT tracking VDDQ × 0.5. |
| Voltage Accuracy | ±0.5% over line/load/temperature - enables tight DDR3 VDDQ/VTT tolerance compliance without external calibration. |
| Current Sensing | Full-differential across DCR with per-phase OC detection and average OC protection - eliminates PCB layout sensitivity to ground bounce. |
| Thermal Compensation | Single NTC-based TM/TCOMP interface with programmable gain - enables real-time load-line adjustment for temperature-dependent VR_HOT and Imon scaling. |
| Efficiency Features | VFDE (variable frequency diode emulation), GDC (gate drive control), and DPM (dynamic phase management) - reduce light-load losses while preserving transient response. |
| PMBus Support | Fully configurable via PMBus: VOUT, OV/UV thresholds, IMON, temperature, duty cycle, and fault status reporting per Section 12 of datasheet. |
Pinout & Package
Package: VFQFPN48, 6×6 mm, 0.4 mm pitch, exposed thermal pad (GND). Compatible with standard reflow profiles and high-density server PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PWM1–PWM3 | Multi-phase PWM outputs | Drive external high-side/low-side drivers or DrMOS; support HiZ strapping for compatibility; PWM3 strap sets 2-phase mode. |
| SPWM | Single-phase PWM output | Drives VTT-phase driver; configurable HiZ via VCC5 pull-up to disable section. |
| CS1P–CS3P / CS1N–CS3N | Multi-phase current sense inputs | Differential inputs per phase; require R-C filter on positive side, Rg + 100 nF to GND on negative side for noise immunity. |
| SCSP / SCSN | Single-phase current sense inputs | Isolated differential pair for VTT current monitoring; same filtering as multi-phase but dedicated path. |
| TM / TCOMP | Thermal monitor interface | TM connects to NTC network; TCOMP sets gain for thermal compensation; shorting TM to GND disables VTT in JMode. |
| VSEN / SVSEN | Remote voltage sense inputs | VSEN for VDDQ, SVSEN for VTT - enable true remote sensing at load point to reject PCB IR drop. |
| SVDATA / SMCLOCK / SMAL# | PMBus interface | Standard SMBus 2.0-compatible interface for configuration, telemetry, and fault logging; supports hot-plug capable systems. |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic Phase Management (DPM) | Automatically scales active phases (3→2→1) under light load to cut switching losses while maintaining loop stability via LTB Technology™. |
| Adaptive Voltage Positioning (AVP) | Programmable load-line droop (V = VREF − I×R) applied independently to VDDQ and VTT - improves system power efficiency without violating DDR3 voltage margins. |
| VFDE & GDC Gate Drive Control | Variable-frequency diode emulation reduces body-diode conduction loss; GDC adjusts dead-time dynamically to minimize shoot-through and conduction loss. |
| Dual Independent Oscillators | Separate ROSC pins (OSC for VDDQ, SOSC for VTT) allow independent frequency tuning - e.g., 500 kHz VDDQ + 300 kHz VTT for optimal efficiency partitioning. |
| Pre-biased Output Management | Supports startup into pre-charged output (e.g., warm-reboot scenarios) without reverse current flow or latch-up - critical for server reliability. |
Applications
| DDR3 Server Memory Rail | VR12 Compliant DIMM Power |
|---|---|
|
Use Scenario: High-density 2U/4U rack servers requiring stable, scalable DDR3 memory power with Intel VR12 compliance and thermal-aware load-line tuning. IC Role / Device Role / Timing Role: Dual-loop VR12 controller managing VDDQ (3-phase) and VTT (1-phase) with synchronized SVID communication and independent fault handling. Use Value: Enables ±0.5% VDDQ accuracy and VTT tracking at ×0.5 ratio - meets JEDEC DDR3-1866 timing margin requirements under full thermal stress. |
Use Scenario: Enterprise storage controllers with dual-rank DDR3 RDIMMs where VTT must track VDDQ precisely during dynamic frequency scaling (DFS). IC Role / Device Role / Timing Role: Programmable SVID endpoint with JMode-configurable voltage positioning and dual remote sense - ensures consistent signal integrity across memory channels. Use Value: Dual independent oscillators (OSC/SOSC) allow VDDQ and VTT to operate at different frequencies optimized for respective load profiles - reducing total system EMI. |
| Thermally Adaptive Memory Supply | High-Availability Server PSU |
|
Use Scenario: Liquid-cooled AI inference servers where memory junction temperature varies >40°C during workload bursts. IC Role / Device Role / Timing Role: Single-NTC thermal monitor (TM/TCOMP) feeding real-time load-line compensation and VR_HOT alarm generation. Use Value: Programmable TCOMP gain enables linear thermal derating of VDDQ droop - maintains memory timing margins while preventing thermal throttling. |
Use Scenario: Carrier-grade telecom servers requiring zero-downtime firmware updates and hot-swap capability. IC Role / Device Role / Timing Role: PMBus-enabled controller supporting READ_IOUT, READ_TEMPERATURE, and fault logging - enables predictive maintenance and BOM traceability. Use Value: Dual VR_RDY signals (VR_RDY/SVR_RDY) provide independent power-good handshaking for VDDQ and VTT rails - essential for phased boot sequences and graceful shutdown. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar VR12 dual-rail memory controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6367CRZ-T | 3+1 VR12 controller with integrated MOSFET drivers; no separate SPWM pin; uses analog VID instead of full PMBus. | Lacks full PMBus telemetry (no READ_IOUT/READ_TEMPERATURE); requires external DAC for AVP tuning. | Choose when board space is constrained and PMBus telemetry is not required for system management. |
| TPS53679RSAT | TI VR12.5/13 dual controller with CSD (current sense digital) interface; supports 4+1 phase; no JMode pin-strapping. | Requires external ADC for thermal monitoring; no single-NTC analog interface; higher pin count (56-QFN). | Choose for VR12.5/13 migration paths or when digital current sensing and higher phase count are needed. |
Compared with ISL6367CRZ-T and TPS53679RSAT, the L6759D uniquely combines full PMBus configurability, analog NTC thermal compensation, JMode flexibility, and VFQFPN48 compactness - making it optimal for cost-sensitive, thermally demanding VR12 server designs requiring field-upgradable settings.
Availability
L6759D is available at Aetrix Electronics and suitable for DDR3 server memory supplies, VR12-compliant DIMM power modules, and thermally adaptive memory rail designs requiring stable component supply and long-term industrial lifecycle support.
Supply support for L6759D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and automotive-grade analog ICs, with broad industrial and datacenter design-in expertise.
The L6759D belongs to ST's VR12 server power controller product line, engineered specifically for high-efficiency, thermally robust DDR3 memory rail regulation in enterprise servers and storage systems.
FAQ
What is the function of the TM and TCOMP pins on the L6759D?
The TM pin connects to an NTC thermistor network to monitor multi-phase section temperature and generate the VR_HOT alarm signal when exceeding TMAX. The TCOMP pin sets the gain for thermal compensation of the load-line droop - adjusting VDDQ output voltage based on sensed temperature. Shorting TM to GND in JMode disables the VTT section, enabling hardware-selectable configuration without software intervention.
How does the L6759D implement adaptive voltage positioning (AVP)?
The L6759D implements AVP by applying a programmable load-line (V = VREF − I×R) to both VDDQ and VTT outputs independently. Droop resistance is set via PMBus commands or pin-strapping (ADDR/IMAX), and current is measured using full-differential DCR sensing. This ensures output voltage decreases linearly with load current - improving system efficiency while staying within DDR3 voltage margin limits.
Can the L6759D support pre-biased output startup?
Yes, the L6759D supports pre-biased output startup through LSLESS (Lossless Startup with External Sense) logic. When enabled, it prevents reverse current flow into the output capacitor during power-on by monitoring SVSEN/VSEN before enabling PWM outputs. This avoids inrush-induced stress on downstream memory components and is essential for server warm-reboot reliability.
What protection features are implemented in the L6759D's multi-phase section?
The multi-phase section includes per-phase and average overcurrent (OC) protection, overvoltage (OV) and undervoltage (UV) detection on FB, feedback disconnection protection, and dual VR_RDY signaling. OC protection uses both peak-current limiting and average-current latching (via ILIM pin), while OV triggers at +175 mV above nominal - all with independent fault latching and recovery modes configurable via PMBus.
L6759D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VR12
- Voltage - Input:
- 10.8V ~ 13.2V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.25V ~ 1.52V
- Operating Temperature:
- 0°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VFQFPN (6x6)
L6759D FAQ
1.How can I place an order for L6759D through Aetrix?
Please submit a Request for Quotation (RFQ) for L6759D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for L6759D reliable?
The price and inventory of L6759D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L6759D is usually 5 days.
3.What payment methods are accepted for L6759D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L6759D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for L6759D?
L6759D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your L6759D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for L6759D?
For technical support, including L6759D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L6759D requirements.
6.How does Aetrix verify that L6759D is sourced from the original manufacturer or authorized distributors?
All L6759D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L6759D meets industry standards.
7.What is the process for return or replacement of L6759D?
All L6759D units undergo pre-shipment inspection (PSI). If there is an issue with L6759D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The L6759D part is unused and in its original packaging.
Return procedure for L6759D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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