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STMicroelectronics L6759DTR
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- Part No.:
- L6759DTR
- Manufacturer:
- STMicroelectronics
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
L6759DTR.pdf
- Description:
- IC REG CTRLR VR12 2OUT 48VFQFPN
- Quantity:
- Payment:
- Shipping:
Inventory:298
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Product details
Overview
L6759DTR from STMicroelectronics is a VR12-compliant dual-phase controller IC for DDR3 memory power delivery in server platforms, featuring 3-phase VDDQ and 1-phase VTT regulation, 25 MHz SVID bus compliance (Rev 1.5), 0.5% output voltage accuracy, and full-differential DCR current sensing.
For engineers reviewing the L6759DTR datasheet, L6759DTR pinout, L6759DTR application, or L6759DTR equivalent, key selection criteria include VR12 SVID interface support, dual independent oscillator control, JMode programmability, VFDE/GDC efficiency optimization, and single-NTC thermal compensation across both phases.
Technical Context
The L6759DTR implements two independent control loops: a 3-phase buck controller for VDDQ with per-phase current monitoring and average/phase-specific overcurrent protection, and a dedicated 1-phase buck controller for VTT that tracks VDDQ at half voltage. It uses LTB Technology™ for fast transient response and stability.
It supports dynamic phase management (DPM), variable frequency diode emulation (VFDE), and gate drive control (GDC) to optimize efficiency across load ranges while maintaining tight voltage positioning via adaptive droop (AVP). Thermal compensation is applied to both sections using a shared NTC network on the TM pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VR12 Compliance | Full SVID Rev 1.5 support at 25 MHz; enables direct communication with Intel VR12 processors for VID updates and telemetry. |
| Output Accuracy | ±0.5% over line/load/temperature; ensures DDR3 VDDQ/VTT voltage stability within JEDEC tolerance limits. |
| Current Sensing | Full-differential DCR sensing per phase; eliminates offset errors and improves current measurement fidelity for accurate load-line implementation. |
| Thermal Compensation | Single NTC input (TM pin) with programmable gain (TCOMP); applies unified thermal derating to both VDDQ and VTT load lines. |
| Oscillators | Dual independent oscillators: OSC (multi-phase, 300–1200 kHz) and SOSC (single-phase, 230 kHz default); enables optimized switching frequency per rail. |
| Protection Features | Dual OV/UV/FB-disconnect, per-phase + average OC, dual VR_RDY signals, and latched ILIM fault; ensures robust DDR3 supply integrity during transients and faults. |
| PMBus Interface | Fully configurable via PMBus commands (READ_VOUT, READ_IOUT, READ_TEMPERATURE, etc.); allows real-time telemetry and dynamic configuration without pin-strapping changes. |
Pinout & Package
VFQFPN48 6×6 mm package with exposed thermal pad (GND-connected); RoHS-compliant, moisture sensitivity level MSL3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PWM1–PWM3 | Multi-phase PWM outputs | Drive external high-side/low-side drivers or DrMOS; support HiZ mode for compatibility; PWM3 strapping configures 2-phase operation. |
| SPWM | Single-phase PWM output | Drives VTT buck stage; HiZ controllable; pulled to VCC5 disables VTT section. |
| CS1P–CS3P / CS1N–CS3N | Multi-phase current sense inputs | Differential DCR sensing per phase; R-C filtering required on positive side, Rg+100nF on negative side for noise immunity. |
| SCSP / SCSN | Single-phase current sense inputs | Differential sensing for VTT rail; identical filtering requirements as multi-phase channels. |
| TM / TCOMP | Thermal monitor interface | TM connects to NTC thermistor; TCOMP sets gain for thermal compensation of load-line slope; shorting TM to GND disables VTT in JMode. |
| SVDATA / SMCLOCK / SMAL# | PMBus interface | Standard SMBus 2.0 compliant interface; supports read/write of all configuration registers and telemetry data. |
| VR_RDY / SVR_RDY | Power-good indicators | Open-drain status signals: VR_RDY for VDDQ, SVR_RDY for VTT; asserted after soft-start completion and cleared on fault. |
Key Features
| Feature | Design Value |
|---|---|
| VR12 SVID Rev 1.5 Interface | Enables seamless integration with Intel VR12 CPUs for dynamic VID scaling, telemetry reporting, and power-state coordination. |
| Dual Independent Oscillators | Allows VDDQ and VTT to operate at different frequencies (e.g., higher FSW for VDDQ, lower for VTT), optimizing efficiency vs. EMI trade-offs. |
| Adaptive Voltage Positioning (AVP) | Automatically adjusts output voltage downward under load per JEDEC DDR3 spec, reducing power loss while maintaining margin. |
| Dynamic Phase Management (DPM) | Reduces active phase count at light loads to cut switching losses, with seamless reactivation during load steps - no performance penalty. |
| VFDE + GDC Efficiency Optimization | VFDE eliminates body-diode conduction loss; GDC dynamically adjusts gate drive strength to minimize driver losses across load range. |
Applications
| DDR3 Server Memory Supply | VR12-Compatible Motherboard Power |
|---|---|
|
Use Scenario: Powering DDR3 DIMMs in dual-socket x86 server motherboards requiring strict VR12 compliance and SVID telemetry. IC Role / Device Role / Timing Role: Dual-rail controller managing VDDQ (1.5 V ±0.75%) and VTT (0.75 V ±0.375%) with synchronized soft-start and independent fault handling. Use Value: Eliminates need for separate controllers; single-chip solution reduces BOM count, PCB area, and design complexity while meeting Intel VR12 validation requirements. |
Use Scenario: High-density 1U/2U rack servers where thermal headroom and power efficiency are constrained by airflow and PSU capacity. IC Role / Device Role / Timing Role: Implements DPM, VFDE, and GDC to maintain >90% peak efficiency across 5–100% load range without sacrificing transient response. Use Value: Reduces system-level power dissipation by up to 12% at light loads versus fixed-phase designs, directly lowering cooling costs and energy consumption. |
| Multi-Phase DDR3 Reference Design | Thermally Compensated Memory Rail |
|
Use Scenario: OEM reference platform development for DDR3-based storage accelerators and NICs requiring validated, production-ready power architecture. IC Role / Device Role / Timing Role: Provides pin-strappable defaults (JMode), PMBus configurability, and comprehensive protection - enabling rapid bring-up and debug. Use Value: Accelerates time-to-market with pre-validated layout guidelines, thermal compensation networks, and fault logging via PMBus READ_STATUS_BYTE. |
Use Scenario: High-ambient-temperature deployments (e.g., edge compute nodes in unconditioned enclosures) where memory rail drift must be minimized. IC Role / Device Role / Timing Role: Uses single NTC on TM pin to apply identical thermal compensation to both VDDQ and VTT load lines, ensuring tracking stability. Use Value: Maintains <±15 mV voltage deviation over 0–90°C ambient, preventing DDR3 timing violations and system instability due to thermal drift. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-rail DDR3 memory controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6367IRZ | Supports VR12.5, not VR12; lacks JMode; uses analog VID instead of SVID; no VFDE or GDC. | Requires external SVID-to-analog translator for VR12 CPU compatibility; less efficient at light loads due to fixed-phase operation. | Select only if upgrading to VR12.5 platforms is planned; verify SVID bridge compatibility before integration. |
| TPS53679RTAR | TI's CSD-compatible dual controller; supports VR12 but with 12-bit DAC resolution (vs. ST's 10-bit); no single-NTC thermal compensation. | Requires two separate NTC networks for VDDQ/VTT; higher component count and calibration effort for thermal tracking. | Prefer when existing TI ecosystem tools (Fusion Digital Power Designer) are mandated; avoid if unified thermal compensation is critical. |
Compared with ISL6367IRZ and TPS53679RTAR, the L6759DTR uniquely combines VR12 SVID-native operation, unified NTC thermal compensation, and integrated efficiency features (VFDE/GDC/DPM) in a single VFQFPN48 package - delivering lower system cost and higher reliability for DDR3 server memory rails.
Availability
L6759DTR is available at Aetrix Electronics and suitable for DDR3 server memory supplies, VR12 motherboard power architectures, and thermally compensated memory rail designs requiring stable component supply and long-term industrial availability.
Supply support for L6759DTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, microcontrollers, and analog ICs for industrial, automotive, and computing markets.
The L6759DTR belongs to ST's VR12-compliant power controller product line, designed specifically to meet Intel's stringent DDR3 memory rail specifications for enterprise servers and high-performance computing platforms.
FAQ
What is the function of the TM and TCOMP pins?
The TM pin connects to an NTC thermistor to monitor multi-phase section temperature and generate the VR_HOT alarm signal. The TCOMP pin sets the gain for thermal compensation applied to the VDDQ and VTT load lines. Shorting TM to GND disables the VTT section in JMode, while pulling TCOMP to GND disables thermal compensation but retains temperature monitoring.
How does JMode affect L6759DTR operation?
JMode is enabled by shorting the TM pin to GND and allows simplified configuration via pin-strapping instead of PMBus. In JMode, the device disables the VTT section, uses fixed IMAX/TMAX values, and ignores SVID commands for VTT control. It is intended for legacy or cost-sensitive designs where full VR12 SVID functionality is not required.
Can L6759DTR support 2-phase VDDQ operation?
Yes - connecting PWM3 to 5 V through a 1 kΩ resistor configures the multi-phase section for 2-phase operation. The internal logic automatically disables PWM2 and adjusts current sharing and protection thresholds accordingly. All other features (DPM, VFDE, AVP) remain fully functional in 2-phase mode.
What protection mechanisms are implemented for VTT rail?
The VTT rail has dedicated OV/UV detection via SVSEN/SFB, per-phase OC protection using SCSP/SCSN differential sensing, and independent VR_RDY assertion (SVR_RDY). It also inherits thermal derating from the TM/TCOMP network and supports pre-biased output startup. Faults trigger latched shutdown unless auto-restart is enabled via PMBus.
L6759DTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Controller, Intel VR12
- Voltage - Input:
- 10.8V ~ 13.2V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.25V ~ 1.52V
- Operating Temperature:
- 0°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VFQFPN (6x6)
L6759DTR FAQ
1.How can I place an order for L6759DTR through Aetrix?
Please submit a Request for Quotation (RFQ) for L6759DTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for L6759DTR reliable?
The price and inventory of L6759DTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L6759DTR is usually 5 days.
3.What payment methods are accepted for L6759DTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L6759DTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for L6759DTR?
L6759DTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your L6759DTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for L6759DTR?
For technical support, including L6759DTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L6759DTR requirements.
6.How does Aetrix verify that L6759DTR is sourced from the original manufacturer or authorized distributors?
All L6759DTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L6759DTR meets industry standards.
7.What is the process for return or replacement of L6759DTR?
All L6759DTR units undergo pre-shipment inspection (PSI). If there is an issue with L6759DTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The L6759DTR part is unused and in its original packaging.
Return procedure for L6759DTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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