STMicroelectronics L6910G
- Part No.:
- L6910G
- Manufacturer:
- STMicroelectronics
- Category:
- DC DC Switching Controllers
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
L6910G.pdf
- Description:
- IC REG CTRLR BUCK 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,199
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Product details
Overview
L6910G from STMicroelectronics is a voltage-mode PWM synchronous buck controller IC designed for high-performance DC-DC conversion from 5V to 12V input buses. It delivers adjustable output down to 0.9V ±1.5%, supports 0–100% duty cycle, integrates 1.3A high-side and 1.1A low-side gate drivers, and features hiccup-mode overcurrent protection, power-good output, and 200kHz–1MHz externally adjustable switching frequency. It is used in memory supply and termination circuits requiring fast transient response and precise low-voltage regulation.
For engineers reviewing the L6910G datasheet, L6910G pinout, L6910G application, or L6910G equivalent, key selection considerations include its SO-16 narrow package, internal 0.9V reference accuracy, oscillator adjustability via RT resistor, synchronous rectification support, and integrated overvoltage crowbar protection using PHASE and OCSET pins.
Technical Context
The L6910G implements voltage-mode PWM control with a 10MHz gain-bandwidth error amplifier and 10V/µs slew rate, enabling high-loop bandwidth for sub-microsecond load transient recovery. Its oscillator allows precise frequency tuning (50kHz–1MHz) via external RT resistor connected to GND or VCC, while maintaining fixed 1.23V bias at the OSC pin.
Current sensing uses rDS(on) of the high-side MOSFET-eliminating sense resistors-and triggers hiccup-mode shutdown when OCSET detects overcurrent. Overvoltage protection activates a crowbar by turning on the low-side MOSFET continuously until fault clearance, with PGOOD asserting only when FB voltage remains within ±10% of EAREF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VREF | 0.9V ±1.5% - enables accurate sub-1V output regulation without external reference |
| fSW Range | 50kHz–1MHz - adjustable via RT resistor; default 200kHz when OSC open |
| IHGATE Peak | 1.3A source - drives high-side N-MOS with minimal gate charge delay |
| ILGATE Peak | 1.1A source - ensures fast low-side turn-on and adaptive dead-time control |
| Duty Cycle | 0%–100% - supports wide VIN/VOUT ratios including 12V→0.9V step-down |
| OVP Threshold | 120% of EAREF - triggers crowbar via LGATE and pulls PGOOD low |
| SS Current | 10µA (normal), 35µA (initial) - sets soft-start ramp time with external capacitor |
Pinout & Package
Package: SO-16 narrow (300 mil), surface-mount, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 VREF | Internal reference output | 0.9V ±1.5% source; requires ≥1nF ceramic bypass; forces hiccup if <0.63V |
| 2 OSC | Oscillator frequency control | Fixed 1.23V node; sink/source current via RT sets fSW; stops oscillation at 50µA injection |
| 3 OCSET | Overcurrent threshold setting | 200µA current sink; sets IOC = 200µA × ROCSET/RDS(on) of high-side MOS |
| 4 SS/INH | Soft-start timing & enable/disable | 10µA ramp current; disable by pulling <0.4V; discharges during UVLO or OVP |
| 5 COMP | Error amplifier output | Compensation node for voltage loop; connects to RC network for stability |
| 6 FB | Inverting input of error amp | Monitors output via resistor divider; determines PGOOD and OVP thresholds |
| 7 GND | Analog ground reference | Reference for all internal analog blocks; must connect to clean PCB signal ground |
| 8 EAREF | Error amp non-inverting input | Accepts 0.9–3V external reference or shorted to VREF; shuts down if <0.65V |
| 9 PGOOD | Open-collector status output | Pulled low if FB outside 88–112% of EAREF; requires external pull-up |
| 10 PHASE | High-side MOS source return | Provides current-sense path for OCSET; monitors VDS of upper MOS |
| 11 HGATE | High-side gate driver output | Drives N-MOS gate via BOOT capacitor; peak 1.3A source capability |
| 12 BOOT | Bootstrap supply for HGATE | Charged via diode from VCC; supplies HGATE when PHASE is low |
| 13 PGND | Power ground | Low-impedance return for LGATE and power stage; must tie near low-side MOS source |
| 14 LGATE | Low-side gate driver output | Directly driven from VCC; 1.1A source; turns on after HGATE turn-off (200ns dead time) |
| 15 VCC | IC supply input | Operates from 5–12V; UVLO thresholds at 4.1V (on)/3.95V (off) |
| 16 N.C. | No internal connection | Not bonded; may float or connect to GND for mechanical stability |
Key Features
| Feature | Design Value |
|---|---|
| Synchronous rectification control | Integrated dual N-MOS drivers with adaptive dead-time prevent shoot-through and reduce conduction losses |
| rDS(on)-based current sensing | Eliminates external current-sense resistor; reduces BOM count and board space while preserving accuracy |
| Hiccup-mode overcurrent protection | Discharges SS capacitor and restarts soft-start after fault clearance-no full power-cycle required |
| Adjustable 0–100% duty cycle | Enables deep step-down (e.g., 12V→0.9V) and 100% conduction for ultra-low dropout operation |
| Internal 0.9V ±1.5% reference | Supports precision low-VOUT regulation without external reference IC or trimming |
Applications
| Memory Supply and Termination | Computer Add-On Cards |
|---|---|
Use Scenario: Providing stable 1.2V/1.5V/1.8V supply and parallel termination for DDR SDRAM, SRAM, and FPGA I/O banks on high-speed memory modules. IC Role / Device Role / Timing Role: Primary synchronous buck controller managing dynamic load transients during burst read/write cycles. Use Value: Fast load transient response (<1µs recovery) and ±1.5% VREF accuracy ensure signal integrity and compliance with JEDEC VDD tolerance specs. | Use Scenario: Generating multiple regulated rails (e.g., 3.3V, 1.2V) on PCIe expansion cards, GPU risers, and industrial I/O add-in boards. IC Role / Device Role / Timing Role: Central DC-DC controller coordinating power sequencing and PGOOD signaling across rail domains. Use Value: Integrated PGOOD and hiccup-mode OCP simplify system-level fault handling and meet PCIe power management requirements. |
| Low-Voltage Distributed DC-DC | Mag-Amp Replacement |
Use Scenario: Local point-of-load (POL) conversion in telecom line cards and server midplanes where 5V/12V backplane rails feed distributed 0.9–3.3V loads. IC Role / Device Role / Timing Role: High-efficiency synchronous buck controller replacing discrete solutions with tight layout constraints. Use Value: SO-16 footprint and 1.3A gate drive allow direct driving of low-RDS(on) MOSFETs-reducing component count vs. driver+controller combos. | Use Scenario: Replacing magnetic amplifiers in multi-output forward converters to regulate secondary-side 1.2V–3.3V outputs. IC Role / Device Role / Timing Role: Secondary-side synchronous rectifier controller synchronized to primary PWM edge via optocoupler or auxiliary winding. Use Value: Eliminates mag-amp core losses and improves cross-regulation; 0–100% duty cycle accommodates variable duty primary topologies. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS40210 | Current-mode control; no integrated gate drivers; requires external high-side driver; 4.5–28V input range | Better suited for wide-input industrial supplies; lacks hiccup-mode OCP and internal 0.9V reference | Select when input exceeds 12V or current-mode loop stability is preferred over voltage-mode speed |
| ISL6208 | Voltage-mode like L6910G; 2A gate drive; supports 3–28V input; includes VID interface for CPU VRMs | Targeted at mobile CPU/GPU VRM applications; adds digital interface not needed in fixed-output systems | Select for programmable output or multi-phase scaling; avoid if simple fixed-output design suffices |
Compared with TPS40210 and ISL6208, the L6910G offers optimal trade-offs for fixed-output, medium-power (≤20A) synchronous buck designs: its integrated 1.3A/1.1A drivers eliminate external drivers, its 0.9V ±1.5% reference simplifies low-VOUT accuracy, and its hiccup-mode OCP provides robust fault recovery without system reset.
Availability
L6910G is available at Aetrix Electronics and suitable for memory supply and termination, computer add-on cards, and low-voltage distributed DC-DC applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for L6910G includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, microcontrollers, and automotive ICs.
The L6910G belongs to ST's high-performance DC-DC controller product line, engineered specifically for synchronous buck topologies in computing, communications, and industrial equipment where precision regulation, fast transient response, and integrated protection are critical.
FAQ
What is the minimum output voltage achievable with the L6910G?
The L6910G supports an output voltage as low as 0.9V ±1.5% when using its internal reference (EAREF tied to VREF). With an external reference up to 3V applied to EAREF, higher output voltages can be set via the FB resistor divider. The 0.9V minimum is guaranteed across temperature and load, making it suitable for modern low-voltage logic and memory rails.
How does the L6910G implement overcurrent protection without a sense resistor?
The L6910G senses overcurrent by monitoring the voltage drop across the high-side MOSFET's rDS(on) using the OCSET pin. An internal 200µA current source flows through an external resistor (ROCS) connected between OCSET and the MOSFET drain. When the rDS(on) × IOUT voltage exceeds ROCS × 200µA, the device enters hiccup mode-discharging the SS capacitor and restarting soft-start after fault clearance.
Can the L6910G operate with 100% duty cycle, and what is its significance?
Yes, the L6910G supports 0% to 100% duty cycle operation. This enables ultra-low dropout regulation-for example, delivering 3.3V from a 3.6V input-or sustaining output during brief input dips without dropout. It also allows use in "lossless" configurations where the high-side MOSFET remains fully on, minimizing conduction loss and improving efficiency at light loads.
What is the role of the PHASE pin beyond gate driving?
The PHASE pin serves three critical functions: (1) return path for the high-side gate driver, (2) current-sense node for OCSET-based overcurrent detection via rDS(on), and (3) feedback point for adaptive dead-time control-ensuring the low-side MOSFET turns on only after the high-side is fully off, preventing shoot-through even with varying MOSFET switching speeds.
L6910G Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 5V ~ 12V
- Frequency - Switching:
- 200kHz
- Duty Cycle (Max):
- 100%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Frequency Control, Phase Control, Power Good, Soft Start
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
L6910G FAQ
1.How can I place an order for L6910G through Aetrix?
Please submit a Request for Quotation (RFQ) for L6910G on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for L6910G reliable?
The price and inventory of L6910G are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L6910G is usually 5 days.
3.What payment methods are accepted for L6910G?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L6910G transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for L6910G?
L6910G orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your L6910G order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for L6910G?
For technical support, including L6910G datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L6910G requirements.
6.How does Aetrix verify that L6910G is sourced from the original manufacturer or authorized distributors?
All L6910G products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L6910G meets industry standards.
7.What is the process for return or replacement of L6910G?
All L6910G units undergo pre-shipment inspection (PSI). If there is an issue with L6910G, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The L6910G part is unused and in its original packaging.
Return procedure for L6910G:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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