STMicroelectronics L6983N33QTR

Overview

L6983N33QTR from STMicroelectronics is a synchronous step-down DC-DC converter delivering up to 3 A DC output current with fixed 3.3 V output, 3.5–38 V input range, 17 μA quiescent current, and QFN16 (3×3 mm) package. It operates in low-noise mode (LNM) for constant-frequency PWM control and supports external clock synchronization - ideal for industrial 24 V bus systems requiring stable, low-ripple power for sensors and always-on nodes.

For engineers reviewing the L6983N33QTR datasheet, L6983N33QTR pinout, L6983N33QTR application, or L6983N33QTR equivalent, key selection criteria include its 200–2300 kHz programmable switching frequency, internal soft-start (1.3 ms), Power Good open-collector output, overvoltage protection (120% V_REF trip), and thermal shutdown at 165 °C - all critical for robust industrial power design.

Technical Context

The L6983N33QTR implements peak current mode control with integrated slope compensation to prevent subharmonic oscillation. Its LNM variant enforces constant-frequency PWM across all load conditions, eliminating frequency modulation artifacts and ensuring predictable EMI behavior.

It features dual ground domains (AGND and PGND), bootstrapped high-side gate drive (100 nF BOOT–SW capacitor), and an internal 3.3 V V_CC LDO regulated from VIN. The EN/CLKIN pin serves as both enable input (1.2 V threshold) and external synchronization interface (200–2200 kHz range) - exclusive to LNM versions.

Key Specifications

Pinout & Package

Package: QFN16 (3 × 3 mm, 0.5 mm pitch) with exposed thermal pad requiring connection to both AGND and PGND for optimal thermal performance and noise isolation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down regulator applications.

Compared with LM61480RQWR and TPS543320RSAR, the L6983N33QTR uniquely combines 3.5–38 V industrial input tolerance, fixed 3.3 V accuracy, external clock synchronization, and 17 μA quiescent current - making it the only option qualified for always-on 24 V bus nodes demanding both low noise and transient resilience.

Availability

L6983N33QTR is available at Aetrix Electronics and suitable for industrial 24 V bus power systems, decentralized sensor nodes, always-on edge controllers, and noise-sensitive instrumentation requiring stable component supply and long-term manufacturability.

Supply support for L6983N33QTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and power management applications.

The L6983 series targets industrial and embedded power conversion, emphasizing wide-input resilience, ultra-low quiescent current, and EMI-aware operation - specifically engineered for DIN-rail controllers, smart sensors, and always-on edge infrastructure.

FAQ

What is the minimum input voltage required for L6983N33QTR to regulate 3.3 V output?

The device requires a minimum input voltage of 3.5 V to maintain regulation. Below this, the internal UVLO circuit disables switching to protect downstream circuitry. At 3.5 V input, the 3.3 V output remains stable with full 3 A capability, though efficiency drops due to reduced headroom across the integrated FETs.

Can the L6983N33QTR operate without an external bootstrap capacitor?

No - a 100 nF ceramic capacitor between BOOT and SW pins is mandatory. This capacitor supplies gate drive voltage for the high-side NMOS during each switching cycle. Omitting it causes immediate failure of high-side conduction, resulting in no output voltage and potential thermal stress on the low-side FET.

How does the EN/CLKIN pin behave during synchronization mode?

When configured for synchronization, the EN/CLKIN pin must be driven by a clean square wave (2.3–2.5 V amplitude, ≥60 ns pulse width) within 200–2200 kHz. The internal logic locks the oscillator to the external clock edge - disabling internal frequency programming via FSW resistor and enforcing strict phase alignment across multiple L6983 devices.

Is the exposed thermal pad electrically connected to any internal node?

Yes - the exposed pad is internally connected to PGND. It must be soldered and tied to both PGND and AGND planes on the PCB using multiple thermal vias. This dual connection ensures low-impedance power ground return while providing a low-resistance path for analog ground reference stability and thermal dissipation.