STMicroelectronics L6995DTR

Overview

L6995DTR from STMicroelectronics is a constant-on-time synchronous step-down DC-DC controller IC designed for high-efficiency, high-differential-input-output conversion in CPU core and I/O bus power supplies. It supports 1.5V–28V input, delivers regulated output down to 0.9V ±1%, integrates lossless valley current limiting via R_DS(on) sensing, and features remote voltage sensing with latched OVP/UVP protection.

For engineers reviewing the L6995DTR datasheet, L6995DTR pinout, L6995DTR application, or L6995DTR equivalent, key selection criteria include its 950 ns typical on-time, 580 ns minimum off-time, 600 µA quiescent current, pulse-skipping light-load mode, and TSSOP20 package with integrated high- and low-side gate drivers capable of >20 A output current.

Technical Context

The L6995DTR implements a hysteretic constant-on-time (COT) control architecture where Ton ∝ V_SENSE/V_OSC, enabling near-constant switching frequency via voltage feed-forward. Its loop closure uses valley regulation at the V_FB node referenced to an internal 0.9 V bandgap, with optional integrator insertion at the INT pin to correct static errors from PCB trace drops and output ripple.

Protection logic includes latched overvoltage (115% V_REF) and undervoltage (69% V_REF) detection sourced from V_SENSE, with fault status signaled via open-drain PGOOD and OVP pins. Anti-cross-conduction timing ensures safe HS/LS MOSFET dead time by monitoring PHASE and LGATE voltages before turn-on transitions.

Key Specifications

Pinout & Package

TSSOP20 package: thermally enhanced, 0.65 mm pitch, 6.5 mm × 4.4 mm body, exposed thermal pad (PGND-connected).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck controller applications.

Compared with TPS54620RGYR and ISL6269CRZ, the L6995DTR offers superior transient response due to its COT architecture and integrated remote sensing, but requires careful bootstrap and gate drive layout; it trades fixed-frequency EMI control for higher light-load efficiency and simpler loop design.

Availability

L6995DTR is available at Aetrix Electronics and suitable for CPU core power, notebook main DC-DC, and networking ASIC power applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for L6995DTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The L6995DTR belongs to ST's high-performance power management controller product line, engineered specifically for high-efficiency, high-transient-response DC-DC conversion in portable computing and communications infrastructure.

FAQ

What is the recommended bootstrap capacitor value for L6995DTR?

A 100 nF X7R ceramic capacitor rated ≥16 V is recommended between BOOT and PHASE pins. This value ensures sufficient charge transfer to sustain high-side gate drive during continuous conduction mode at maximum duty cycle, while minimizing voltage ripple that could trigger premature HS turn-off.

How does the L6995DTR implement remote sensing, and what is its accuracy impact?

The L6995DTR uses dedicated VSENSE and GNDSENSE pins to close the feedback loop at the load terminals. This compensates for voltage drops across PCB traces and connectors, reducing static regulation error to within ±5 mV even with 50 mΩ total path resistance-verified per Figure 4 and Section 1.2 of the datasheet.

Can the L6995DTR operate without the integrator (INT pin)?

Yes - the INT pin can be shorted to VREF to disable the integrator. In this configuration, regulation relies solely on the VFB-to-VREF comparator, which provides adequate performance for applications with low trace resistance and minimal output ripple (<50 mV_pp), as confirmed in the "Closing the loop" section (page 7).

What happens during an overvoltage fault, and how is recovery performed?

During overvoltage, the OVP pin goes high and PGOOD goes low while the device latches: HS FET turns off, LS FET remains on. Recovery requires cycling SHDN (pulling low then high) or removing and reapplying VCC - no automatic reset occurs, ensuring fault persistence until deliberate intervention per Section 1.6.