STMicroelectronics L6997S
- Part No.:
- L6997S
- Manufacturer:
- STMicroelectronics
- Category:
- DC DC Switching Controllers
- Package:
- 20-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
L6997S.pdf
- Description:
- IC REG CTRLR BUCK 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,539
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
L6997S from STMicroelectronics is a constant-on-time synchronous step-down controller IC for low-voltage DC/DC conversion, supporting 1V–35V input and regulating down to 0.6V ±1% reference output with lossless valley current limiting, remote sensing, and latched OVP/UVP protection. It drives external high- and low-side MOSFETs in buck topologies for CPU, DSP, and memory power supplies in networking and mobile applications.
For engineers reviewing the L6997S datasheet, L6997S pinout, L6997S application, or L6997S equivalent, key selection criteria include its 0.6V reference accuracy, selectable sinking mode, 600µA quiescent current, pulse-skipping at light loads, and compatibility with >20A output designs using external FETs and bootstrap gate drive.
Technical Context
The L6997S implements a voltage-feed-forward constant-on-time (COT) control architecture where Ton = KOSC × VSENSE/VOSC + τ, enabling near-constant switching frequency across wide input ranges and ultrafast load transient response. Its hysteretic loop lacks an internal clock and initiates switching only when VFB < VREF, minimum off-time has elapsed, and current limit is not active.
Loop stability is enhanced via optional integrator insertion (INT–VFB short + capacitor to VOUT), which adds a DC pole to correct static error from PCB trace drops and output ripple; internal clamping (VREF−50mV to VREF+150mV) limits overshoot during transients. The zero-crossing comparator enables natural PFM operation below ~50% of inductor ripple current.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VREF | 0.6 V ±1% - sets precise output regulation point; supports sub-1V core rails for modern processors. |
| VIN Range | 1 V to 35 V - accommodates wide-input industrial and telecom bus voltages while maintaining regulation. |
| IQ (VCC) | 600 µA typical - enables low-power standby modes without sacrificing startup reliability. |
| Current Limit | Lossless valley sensing via RDS(on) - eliminates sense resistor, preserves efficiency, and supports bidirectional (sinking) mode. |
| Topology | Constant-on-time with feed-forward - delivers <10 µs load transient recovery and input-voltage-invariant frequency tuning. |
| Protections | Latched OVP/UVP on VSENSE, PGOOD open-drain status, and anti-cross-conduction drivers - ensures safe shutdown under fault conditions. |
| Efficiency | 94% @ 3.3 V → 2.5 V - achieved via low-driver losses, adaptive dead-time control, and PFM at light loads. |
Pinout & Package
The L6997S is housed in a thermally enhanced TSSOP20 package (4.4 mm × 6.5 mm, 0.65 mm pitch) with exposed thermal pad for improved power dissipation in high-current DC/DC modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 NOSKIP | Mode select | Connect to VCC to disable pulse skipping and enforce continuous conduction mode. |
| 2 GNDSENSE | Remote ground reference | Compensates for PCB trace IR drop between regulator output and load ground point. |
| 3 INT | Integrator output | Enables DC error correction when shorted to VFB and connected via capacitor to VOUT. |
| 4 VSENSE | OVP/UVP monitor & feedback | Detects over/undervoltage relative to VREF; provides integrator input and feed-forward path. |
| 5 VCC | Main supply rail | 3–5.5 V bias for logic and gate drivers; powers internal reference and comparators. |
| 6 GND | Signal ground | Reference for analog circuitry; separate from PGND to minimize noise coupling. |
| 7 VREF | Precision reference | 0.6 V ±1% bandgap source; capable of sourcing/sinking 250 µA for external filtering. |
| 8 VFB | PWM comparator input | Negative input of error amplifier; tied to VSENSE or INT to close regulation loop. |
| 9 OSC | Voltage feed-forward input | Accepts resistive divider from VIN to set stable fSW; must be 50 mV–1 V for linearity. |
| 10 SS | Soft-start ramp | 5 µA current source charges external capacitor; controls current limit ramp and disables protections until 1 V. |
| 11 ILIM | Current limit threshold | Voltage set by external RILIM to GND; defines valley current limit with ±2% accuracy. |
| 12 SHDN | Enable/disable control | Logic-low disables all drivers and internal circuitry; requires pull-up or active drive. |
| 13 OVP | Fault indicator | Open-drain output pulled high externally during overvoltage latch condition. |
| 14 PGOOD | Power-good status | Open-drain output pulled high when VOUT is within 89–110% of target; pulled low on fault. |
| 15 PGND | Power ground return | Low-side driver return path; isolated from signal GND to reduce switching noise injection. |
| 16 LGATE | Low-side driver output | Drives LS MOSFET gate; rise/fall times ≤90 ns into 14 nF load at 3.3 V. |
| 17 VDR | LS driver supply | 3–5.5 V supply for low-side gate driver; decoupling required near pin. |
| 18 PHASE | HS driver return | Floating return for high-side driver; connects to switch node between HS/LS FETs. |
| 19 HGATE | High-side driver output | Drives HS MOSFET gate; rise/fall times ≤100 ns into 7 nF load at 3.3 V. |
| 20 BOOT | Bootstrap supply | Charged via external diode/capacitor; supplies floating HS driver during conduction. |
Key Features
| Feature | Design Value |
|---|---|
| Constant-on-time control | Delivers <10 µs load transient recovery without compensation network redesign. |
| Lossless valley current limit | Eliminates power-wasting sense resistor while supporting bidirectional (sink) current mode. |
| Remote sensing (GNDSENSE + VSENSE) | Corrects up to 50 mV of static error from PCB trace resistance between output cap and load. |
| Pulse-skipping at light loads | Reduces IQ to ~600 µA and improves light-load efficiency by disabling switching cycles. |
| Latched OVP/UVP with PGOOD | Ensures system-level safety by halting switching and asserting fault signals until manual reset. |
Applications
| Networking Power Modules | Mobile Baseband Processors |
|---|---|
Use Scenario: Regulating 1.2 V/15 A supply for Ethernet PHY and switch ASICs in compact 1U rack units. IC Role / Device Role / Timing Role: Primary synchronous buck controller managing gate timing, current limiting, and OVP latching. Use Value: Remote sensing compensates for 30 mΩ board trace resistance; COT topology maintains <±15 mV output deviation during 8 A/µs load steps. | Use Scenario: Generating 0.85 V core voltage for LTE modem SoCs in battery-powered handheld devices. IC Role / Device Role / Timing Role: Adaptive step-down controller enabling PFM mode below 200 mA to extend battery runtime. Use Value: 600 µA quiescent current and pulse-skipping reduce no-load power to <1.5 mW; 0.6 V reference ensures accurate low-VOUT scaling. |
| CPU Voltage Regulator Modules | DSP Memory Subsystems |
Use Scenario: Delivering dynamically scaled 0.7–1.3 V/25 A output for x86 microprocessors in embedded industrial controllers. IC Role / Device Role / Timing Role: High-current buck controller with integrator loop for tight DC regulation under variable thermal load. Use Value: INT–VFB integrator reduces static error to <5 mV despite 100 mV peak-to-peak output ripple; latched UVP prevents brownout crashes. | Use Scenario: Supplying 1.5 V DDR3 termination and 1.2 V I/O rails for multi-core DSPs in radar signal processing boards. IC Role / Device Role / Timing Role: Dual-rail controller coordinating sequencing via SHDN and PGOOD handshaking. Use Value: Independent OVP/UVP on VSENSE detects rail collapse before data corruption; PGND isolation minimizes switching noise on sensitive analog paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54620 | Fixed-frequency current-mode PWM (not COT); integrated FETs (6 A max); no remote GND sensing. | Targeted at mid-power integrated solutions; unsuitable for >20 A or ultra-fast transient applications. | Select when board space is constrained and output current ≤6 A; avoid for high-transient networking modules. |
| ISL8113 | Voltage-mode COT controller; supports 40 V input; no sinking mode or integrator loop; different pinout. | Designed for higher-voltage industrial DC/DC; lacks VSENSE-based OVP latching and GNDSENSE correction. | Prefer for 36 V input systems requiring fast transients but no bidirectional current capability or precision remote sensing. |
Compared with TPS54620 and ISL8113, the L6997S uniquely combines lossless valley current limiting, remote ground sensing, and integrator-based DC error correction-making it optimal for high-accuracy, high-current, low-voltage CPU/DSP supplies where board-level IR drop and ripple-induced static error must be actively suppressed.
Availability
L6997S is available at Aetrix Electronics and suitable for networking power modules, mobile baseband processor supplies, and CPU voltage regulator modules requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for L6997S includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, power, MCU, and sensor solutions for industrial, automotive, and consumer markets.
The L6997S belongs to ST's high-efficiency DC/DC controller product line, engineered specifically for low-voltage, high-current point-of-load regulation in space-constrained networking and mobile platforms demanding fast transient response and precision output accuracy.
FAQ
What is the minimum recommended output voltage and how is it stabilized?
The L6997S supports a minimum regulated output voltage of 0.6 V, defined by its internal ±1% precision bandgap reference (VREF). Stability at this level is achieved through remote sensing (VSENSE and GNDSENSE), integrator loop correction (INT–VFB), and constant-on-time control that maintains regulation even with large input variations or PCB trace resistance up to 50 mΩ.
How does the lossless current limit function without a sense resistor?
The L6997S senses inductor current by monitoring the voltage drop across the low-side MOSFET's RDS(on) using the ILIM pin. An external resistor (RILIM) sets the threshold voltage; the internal comparator triggers when VILIM exceeds this value, enforcing valley current limiting without dissipative external components-preserving efficiency and thermal margin.
Can the L6997S operate in forced continuous conduction mode (FCCM)?
Yes-connecting the NOSKIP pin to VCC disables pulse skipping and forces continuous conduction mode. This eliminates low-frequency beat notes in noise-sensitive applications and ensures deterministic switching frequency, though at the cost of reduced light-load efficiency compared to native PFM operation.
What are the critical layout requirements for reliable boot capacitor operation?
A low-ESR ceramic boot capacitor (typically 0.1 µF) must be placed within 3 mm of the BOOT and PHASE pins, with a Schottky diode (e.g., BAT54) connecting VCC to BOOT. The PHASE trace must be short and wide to minimize inductance; insufficient boot charge causes HGATE dropout and shoot-through risk due to inadequate high-side driver voltage during switching transitions.
L6997S Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Frequency - Switching:
- -
- Duty Cycle (Max):
- -
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Phase Control, Power Good, Soft Start
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP
L6997S FAQ
1.How can I place an order for L6997S through Aetrix?
Please submit a Request for Quotation (RFQ) for L6997S on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for L6997S reliable?
The price and inventory of L6997S are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L6997S is usually 5 days.
3.What payment methods are accepted for L6997S?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L6997S transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for L6997S?
L6997S orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your L6997S order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for L6997S?
For technical support, including L6997S datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L6997S requirements.
6.How does Aetrix verify that L6997S is sourced from the original manufacturer or authorized distributors?
All L6997S products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L6997S meets industry standards.
7.What is the process for return or replacement of L6997S?
All L6997S units undergo pre-shipment inspection (PSI). If there is an issue with L6997S, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The L6997S part is unused and in its original packaging.
Return procedure for L6997S:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
L6997S Tags

-
UCC28C45DR
Texas Instruments

-
UCC28C40DR
Texas Instruments

-
UCC28C43DR
Texas Instruments

-
ZXSC410E6TA
Diodes Incorporated
-
LM3524DMX/NOPB
Texas Instruments
-
LM3489MMX/NOPB
Texas Instruments

-
MIC2102YML-TR
Microchip Technology

-
LM5148RGYR
Texas Instruments
-
TL598CDR
Texas Instruments

-
LM5155DSSR
Texas Instruments

-
LM25085MYX/NOPB
Texas Instruments

-
UCC2813DTR-0
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

