STMicroelectronics L9961TR
- Part No.:
- L9961TR
- Manufacturer:
- STMicroelectronics
- Category:
- Battery Management
- Package:
- 32-TFQFN Exposed Pad
- Datasheet:
-
L9961TR.pdf
- Description:
- CHIP FOR CONSUMER BATTERY MANAGE
- Quantity:
- Payment:

- Shipping:

Inventory:2,319
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Product details
Overview
L9961TR from STMicroelectronics is a highly integrated battery monitor and protector IC for 3–5 series Li-ion/Li-polymer packs. It performs ratiometric cell voltage measurement (±15 mV error, 12-bit), stack voltage monitoring with plausibility check, ±0.8% gain-accurate NTC-based temperature sensing, bidirectional current measurement (16-bit, 0.1% FS error), Coulomb counting, and active cell balancing up to 70 mA per cell - all while supporting pack relay control via dual HS/LS predrivers and fuse management. Used in cordless power tools and e-bikes.
For engineers reviewing the L9961TR datasheet, L9961TR pinout, L9961TR application, or L9961TR equivalent, key selection criteria include its 2 μA shipment-mode current, integrated 3.3 V/35 mA VREG LDO, I²C-configurable protection thresholds, hotplug-robust architecture, and AEC-Q100-qualified safety features for battery pack systems requiring ASIL-B–compatible monitoring.
Technical Context
The L9961TR implements a multi-stage ADC architecture: a 12-bit SD-ADC for cell and stack voltage with programmable scan loop timing, and a separate 16-bit SD-ADC for high-accuracy current sensing with continuous Coulomb integration. Its internal charge pump (VCP output) enables gate driving of external high-side N-channel MOSFETs without bootstrap components.
Protection logic runs autonomously across three operational states - SHIPMENT (2 μA), STANDBY (3 μA with VREG active), and NORMAL - with configurable UV/OV, OT/UT, and overcurrent/short-circuit triggers. Critical configurations (e.g., thresholds, balancing enable) are stored in embedded NVM to survive deep sleep cycles.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Cell count support | 3 to 5 series Li-ion/Li-polymer cells - defines maximum pack voltage range (up to 25 V VB). |
| Voltage measurement accuracy | ±15 mV max error (1.5–4.5 V range, −40 °C to 105 °C) - ensures reliable cell-level SOC estimation and balancing decisions. |
| Current measurement resolution | 16-bit signed, 0.1% full-scale error at 25 °C - enables precise Coulomb counting and discharge/charge termination. |
| Standby current | 3 μA with VREG active - sustains MCU power during low-duty-cycle monitoring without draining pack. |
| Integrated LDO output | 3.3 V ±3%, 35 mA capable - powers external MCU and LEDs directly, eliminating need for discrete regulator. |
| Operating junction temp | −40 °C to +120 °C - supports operation in harsh environments like power tool battery packs and UPS enclosures. |
| I²C interface | Standard-mode (100 kHz) and fast-mode (400 kHz) compatible - enables real-time SOC/SOH updates and dynamic threshold reconfiguration. |
| Cell balancing current | Up to 70 mA per cell, simultaneous activation - corrects cell imbalance without thermal runaway risk in compact form factor. |
Pinout & Package
VFQFPN32 (5 mm × 5 mm × 1.0 mm, 0.5 mm pitch) package with wettable flanks for automated optical inspection (AOI). Exposed thermal pad improves thermal dissipation in high-current battery monitoring applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| C0–C5 | Cell voltage sense inputs | Differential analog inputs for measuring individual cell voltages (C0 = cell 1 negative, C1–C5 = cell 1–5 positive terminals). |
| ISENSEP/ISENSEM | Current sense ADC inputs | High-precision differential inputs for shunt-based bidirectional current measurement (±200 mV common-mode, ±300 mV differential range). |
| NTC/OD | NTC thermistor interface | NTC connects between NTC and GND; OD provides programmable pull-down to ground for ratiometric temperature measurement. |
| CHG/DCHG/VSC/VSD | Pre-driver outputs | Four analog outputs controlling external N-MOSFET gates (CHG/VSC for charge path, DCHG/VSD for discharge path) with HS/LS configuration flexibility. |
| FUSE | Fuse driver output | Analog/digital output triggering external fuse activation (e.g., pyro fuse) upon critical fault detection. |
| SCL/SDA/RDY/FAULTN | I²C & status signals | SCL/SDA for configuration/data; RDY indicates state transition completion; FAULTN is open-drain fault indicator and CHG/DCHG shutdown trigger. |
| VREG | Regulated power output | 3.3 V LDO output powering MCU and peripherals - remains active in STANDBY mode for low-power wake-up capability. |
| WAKEUP/NSHIP | State transition inputs | WAKEUP wakes from STANDBY; NSHIP wakes from SHIPMENT - both use internal pull-downs and digital filtering (40 μs / 20 μs) to reject noise. |
Key Features
| Feature | Design Value |
|---|---|
| Triple-state power management | SHIPMENT (2 μA), STANDBY (3 μA with VREG), NORMAL - enables years of shelf life and rapid system wake-up with deterministic timing (TSHIP2NORMAL = 5 ms). |
| Autonomous protection engine | Dedicated hardware comparators for OV/UV/OT/UT/OCC/SC - operate independently of MCU, ensuring fail-safe response even during firmware lockup. |
| Embedded NVM configuration storage | Retains user-defined thresholds, balancing settings, and fault masks across power cycles - eliminates boot-time I²C reprogramming overhead. |
| Charge pump-assisted gate drive | VCP output (VB+12 V) enables direct drive of high-side N-MOSFETs without external bootstrap circuitry - simplifies PCB layout and improves reliability. |
| Hotplug-robust I/O architecture | All analog inputs (C0–C5, NTC, ISENSE) and digital pins (SCL/SDA/FAULTN) rated for ±2 kV HBM ESD and tolerate transient slopes up to 1 V/μs on VB - prevents latch-up during pack insertion/removal. |
Applications
| Power Tool Battery Packs | UPS Backup Energy Systems |
|---|---|
Use Scenario: Cordless drill/driver battery packs with 4-series Li-ion cells operating at 14.8 V nominal, subjected to high pulse currents (>30 A) and ambient temperatures up to 70 °C. IC Role / Device Role / Timing Role: Primary battery monitor and protector - performs cyclic cell voltage scanning every 10 ms, detects overcurrent within 1 μs, and triggers DCHG MOSFET shutdown within 200 ns of short-circuit event. Use Value: Enables safe high-power delivery while extending pack life via precision cell balancing (±15 mV accuracy) and thermal derating based on NTC readings with ±0.8% gain error. | Use Scenario: Rack-mounted 48 V (13S) UPS modules using 5-series sub-packs, requiring seamless switchover between AC and battery modes with <10 ms interruption. IC Role / Device Role / Timing Role: Sub-pack level supervisor - monitors individual 5-cell stacks, validates stack voltage vs. summed cell voltages (plausibility check), and coordinates relay sequencing via dual predrivers to prevent backfeed. Use Value: Ensures redundancy-aware protection: FAULTN_SAFE asserts on critical faults (e.g., fuse blow), while FAULTN handles non-critical events (e.g., temporary OV), enabling graded system response. |
| E-Bike Battery Management | Medical Portable Defibrillator Packs |
Use Scenario: 36 V (10S) e-bike battery with integrated BMS, exposed to vibration, humidity, and frequent partial charging cycles. IC Role / Device Role / Timing Role: Core analog front-end - measures cell voltages, pack current (for SOC), and NTC temperature (for charge rate limiting), then reports data via I²C to host MCU running ISO 26262-compliant software. Use Value: Supports functional safety: embedded NVM stores calibrated parameters, and triple-state operation (with 2 μA shipment mode) meets IEC 62304 power-off requirements for long-term storage compliance. | Use Scenario: Lithium-ion battery packs in portable AED devices, where reliability, shelf life (>5 years), and immediate readiness after storage are critical. IC Role / Device Role / Timing Role: Safety-critical pack guardian - maintains ultra-low 2 μA shipment current during storage, wakes instantly on NSHIP assertion, and validates all protections before enabling therapy delivery. Use Value: Guarantees first-use reliability: VREG stabilizes in 5 ms (TSHIP2NORMAL), I²C is ready in 15 ms (TI2C_READY), and all ADCs complete initial calibration before enabling charge/discharge paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar battery monitoring and protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| BQ7695200RSMR | 16-cell support, integrated FET drivers, no charge pump; higher quiescent current (12 μA standby) | Targets larger packs (e.g., EV traction); lacks VFQFPN32 footprint and hotplug robustness specs | Select for >5S systems needing higher integration; avoid if space-constrained or requiring 2 μA shipment mode. |
| MAX17853GCM+ | 14-bit cell ADC (±2 mV typical), daisy-chain capable, no integrated VREG LDO | Designed for modular BMS stacks; requires external 3.3 V supply and adds complexity for single-pack designs | Choose when building scalable multi-pack systems; not suitable as drop-in replacement due to missing VREG and different pinout. |
Compared with BQ7695200RSMR and MAX17853GCM+, the L9961TR delivers superior ultra-low-power operation (2 μA shipment), monolithic 3.3 V regulation, and VFQFPN32 packaging ideal for compact power tool and medical battery packs - making it optimal where size, shelf life, and self-contained power are design priorities.
Availability
L9961TR is available at Aetrix Electronics and suitable for cordless power tools, backup energy storage systems, and light electric vehicles requiring stable component supply, long-term lifecycle support, and automotive-grade reliability.
Supply support for L9961TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and automotive-grade analog products.
The L9961TR belongs to ST's battery management portfolio, engineered specifically for high-reliability, space-constrained Li-ion pack applications demanding ultra-low quiescent current, integrated protection logic, and functional safety-ready architecture.
FAQ
What is the minimum external capacitance required on the VREG pin?
A 4.7 µF ceramic capacitor (±20% tolerance) is mandatory on the VREG pin for stability and transient response, as specified in Table 8 of DS14012 Rev 7. This value ensures proper load regulation during STANDBY-to-NORMAL transitions and supports the 15 mA peak current (IWAKEMAX) needed for MCU wake-up within 1 ms.
Does the L9961TR support daisy-chaining for multi-pack systems?
No, the L9961TR does not support daisy-chaining. It is designed as a single-pack monitor with dedicated I²C interface (SCL/SDA) and local fault signaling (FAULTN, FAULTN_SAFE). Multi-pack architectures require independent I²C buses or host MCU arbitration - unlike ST's L9963 family, which includes dedicated daisy-chain pins.
How is cell balancing triggered and controlled?
Cell balancing is software-controlled via I²C register writes (BAL_EN bit in CONFIG1 register) and can be activated simultaneously on all enabled cells. Balancing current is fixed at up to 70 mA per cell using internal switches; no external balancing resistors are required. The IC automatically disables balancing if cell voltage drops below UV threshold or temperature exceeds OT limit.
What protection functions remain active in SHIPMENT mode?
In SHIPMENT mode, only the NSHIP wake-up detector and basic VREG UV monitoring remain active. All ADC conversions, current sensing, temperature measurement, balancing, and predriver outputs are disabled. The 2 μA consumption is achieved by powering down all analog blocks except the NSHIP comparator and its 20 μs filter circuit.
L9961TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 32-TFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Multi-Function Controller
- Battery Chemistry:
- Lithium Ion/Polymer
- Number of Cells:
- 3 ~ 5
- Fault Protection:
- Over Current, Over Temperature, Over/Under Voltage, Reverse Battery, Short Circuit
- Interface:
- I2C
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount, Wettable Flank
- Supplier Device Package:
- 32-VFQFPN (5x5)
L9961TR FAQ
1.How can I place an order for L9961TR through Aetrix?
Please submit a Request for Quotation (RFQ) for L9961TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for L9961TR reliable?
The price and inventory of L9961TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for L9961TR is usually 5 days.
3.What payment methods are accepted for L9961TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for L9961TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for L9961TR?
L9961TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your L9961TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for L9961TR?
For technical support, including L9961TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your L9961TR requirements.
6.How does Aetrix verify that L9961TR is sourced from the original manufacturer or authorized distributors?
All L9961TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that L9961TR meets industry standards.
7.What is the process for return or replacement of L9961TR?
All L9961TR units undergo pre-shipment inspection (PSI). If there is an issue with L9961TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The L9961TR part is unused and in its original packaging.
Return procedure for L9961TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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