STMicroelectronics LD39050PUR

Overview

LD39050PUR from STMicroelectronics is a 500 mA ultra-low-dropout linear voltage regulator with 200 mV typical dropout at full load, 20 µA typical quiescent current at no load, ±2.0% output voltage tolerance at 25 °C, and operation across 1.5 V to 5.5 V input range. It delivers stable low-noise power for battery-powered systems requiring high efficiency and minimal standby consumption.

For engineers reviewing the LD39050PUR datasheet, LD39050PUR pinout, LD39050PUR application, or LD39050PUR equivalent, key selection criteria include dropout voltage under 500 mA load, sub-1 µA shutdown current, ceramic capacitor compatibility (1 µF C_OUT), Power Good signaling, and thermal/short-circuit protection in DFN6 (2x2 mm) package.

Technical Context

The LD39050PUR implements a PMOS pass transistor architecture enabling ultra-low dropout and near-zero reverse current during shutdown. Its bandgap reference and error amplifier support precise output regulation across –40 °C to 125 °C junction temperature, with internal current limiting and thermal shutdown at 160 °C (20 °C hysteresis).

It integrates an open-drain Power Good (PG) output that asserts high when V_OUT reaches 92% of nominal and deasserts at 80%, plus logic-controlled enable (EN) with 0.4 V low / 0.9 V high thresholds. Supply voltage rejection is 65 dB at 1 kHz and remains ≥62 dB up to 10 kHz.

Key Specifications

Pinout & Package

LD39050PUR uses the DFN6 (2x2 mm) package with exposed thermal pad, requiring GND connection for optimal thermal performance and EMI suppression. Pin numbering follows top-view orientation per STMicroelectronics DocID15470 Rev 5.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with XC6210B182MR-G and RT9080AL, LD39050PUR uniquely combines 500 mA capability, 200 mV dropout, integrated PG, and 1 µA shutdown in a thermally optimized DFN6 (2x2 mm), making it optimal for high-reliability, feature-complete LDO implementations.

Availability

LD39050PUR is available at Aetrix Electronics and suitable for mobile power management, wearable sensor hubs, industrial IoT nodes, and automotive infotainment cores requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LD39050PUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and MEMS products for industrial, automotive, and consumer markets.

The LD39050 belongs to ST's high-performance LDO portfolio targeting ultra-low-power, low-noise, and high-accuracy applications in battery-operated and thermally constrained systems.

FAQ

What is the minimum input voltage required for LD39050PUR to regulate a 1.2 V output?

The LD39050PUR requires a minimum input voltage of 1.5 V per datasheet specification. For a 1.2 V output, the absolute minimum VIN is V_OUT + V_DROP = 1.2 V + 0.2 V = 1.4 V, but the device is not characterized below 1.5 V input. Therefore, 1.5 V is the guaranteed functional lower limit regardless of output voltage setting.

Can LD39050PUR operate with a 0.5 µF output capacitor?

No. The LD39050PUR is designed and characterized for stability with 1 µF to 22 µF ceramic capacitors. Using 0.5 µF violates the minimum capacitance requirement and risks oscillation or poor transient response, as confirmed in Figure 33–34 of the datasheet showing instability below 1 µF.

Does LD39050PUR support adjustable output voltages?

No. LD39050PUR is the fixed-output variant (as indicated by "PUR" suffix and DFN6 (2x2 mm) pinout with N.C. on Pin 6). Adjustable versions (e.g., LD39050PU33R) use Pin 5 as ADJ and require external resistor dividers; this part has no ADJ pin and delivers factory-set V_OUT.

How does the Power Good (PG) pin behave during startup and dropout?

The PG pin is open-drain and asserts high when V_OUT rises above 92% of its nominal value and deasserts (pulls low) when V_OUT falls to 80%. During startup, PG remains low until regulation is achieved; during input dropout, PG deasserts before V_OUT collapses, providing early warning for system-level fault handling.