STMicroelectronics LD56050DPU105R

Overview

LD56050DPU105R from STMicroelectronics is a 1.05 V, 500 mA ultra-low-dropout linear regulator with NMOS pass transistor and dedicated bias supply (VBIAS) pin, delivering 80 mV typical dropout at full load and ±0.5% output accuracy at 25 °C. It features logic-controlled shutdown (<0.1 µA standby), active output discharge, thermal shutdown (160 °C), and foldback current limiting-designed for space-constrained, battery-powered mobile and imaging systems.

For engineers reviewing the LD56050DPU105R datasheet, LD56050DPU105R pinout, LD56050DPU105R application, or LD56050DPU105R equivalent, key selection considerations include VBIAS voltage dependency (≥VOUT + 1.4 V), DFN4 1.2 × 1.2 mm package layout constraints, output discharge MOSFET timing, and stability with 1 µF–22 µF ceramic output capacitors.

Technical Context

The LD56050DPU105R employs an NMOS pass element whose gate is driven by a separate VBIAS rail-enabling ultra-low dropout even when VIN approaches VOUT (e.g., 1.05 V output from 1.15 V input). This architecture decouples control circuitry biasing from the main power path, improving regulation under low VIN conditions.

It integrates dual protection: thermal shutdown with 20 °C hysteresis and foldback current limiting (ISC = 365–500 mA at VOUT = 0), plus an internal discharge MOSFET (RON = 110 Ω) activated on EN low to rapidly deplete output capacitance-critical for sequencing in multi-rail portable systems.

Key Specifications

Pinout & Package

LD56050DPU105R is housed in a thermally enhanced DFN4 1.2 × 1.2 mm package (0.45 mm height, 4-pin, exposed thermal pad), optimized for high-density PCB layouts in portable electronics. Pin 1 is bottom-left (as viewed from top).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-dropout LDO applications.

Compared with XC6210B102MR-G and RT9080AL-105GJ6F, LD56050DPU105R uniquely supports sub-1.1 V operation via VBIAS, delivers lowest dropout (80 mV), and provides integrated discharge-making it optimal for next-gen compact, battery-sensitive designs where headroom and sequencing are constrained.

Availability

LD56050DPU105R is available at Aetrix Electronics and suitable for mobile phones, tablets, battery-powered wearables, and camera modules requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for LD56050DPU105R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in power management, analog, MEMS, and microcontroller technologies for industrial, automotive, and consumer markets.

The LD56050 belongs to ST's ultra-low-IQ, ultra-low-dropout LDO product line-engineered specifically for space- and energy-constrained portable electronics where minimal voltage headroom, rapid sequencing, and robust protection are mandatory.

FAQ

What is the minimum required VBIAS voltage for LD56050DPU105R at 1.05 V output?

The minimum VBIAS voltage is the greater of 2.4 V or VOUT + 1.4 V. For LD56050DPU105R (1.05 V output), this equals 2.45 V. The datasheet specifies 2.4 V min. for VOUT ≤ 1 V and VOUT + 1.4 V for VOUT > 1 V, with 1.6 V UVLO threshold and 0.2 V hysteresis. Operation below this violates bias circuit functionality and risks regulation failure.

Can LD56050DPU105R operate with VIN = VOUT (i.e., 1.05 V input)?

No. Minimum operating VIN is VOUT + VDROP. At 500 mA, typical dropout is 80 mV, so minimum VIN is ~1.13 V (1.05 V + 0.08 V). Absolute minimum VIN per absolute maximum ratings is –0.3 V, but functional operation requires VIN ≥ VOUT + VDROP (27–250 mV depending on load and VBIAS). Below this, regulation is lost and output collapses.

Is an external pull-up resistor required on the EN pin?

Yes. The EN pin has no internal pull-up; leaving it floating risks undefined behavior. A 100 kΩ–1 MΩ pull-up to VIN or VBIAS is recommended to ensure reliable high-state activation. Input leakage is only 400 nA, so minimal current is drawn-critical for battery longevity in always-on systems.

What output capacitor ESR range ensures stability for LD56050DPU105R?

The control loop is stable with ceramic capacitors (X5R/X7R) having ESR between 3 mΩ and 300 mΩ. Capacitance must be 1.0–22 µF. Stability depends on maintaining ESR within this band across temperature, voltage, and aging-X5R/X7R types are explicitly recommended because they retain both capacitance and ESR in spec over –40 °C to 85 °C.