STMicroelectronics LD56050DPU115R

Overview

LD56050DPU115R from STMicroelectronics is a 500 mA ultra-low-dropout linear voltage regulator with NMOS pass transistor architecture, bias supply pin (VBIAS), and active output discharge. It delivers 1.15 V output with ±0.5% accuracy at 25 °C and ±1.5% over temperature, achieves 80 mV dropout at 500 mA, and operates from 0.8 V to 5.5 V input - ideal for powering core logic in space-constrained mobile phone baseband ICs.

For engineers reviewing the LD56050DPU115R datasheet, LD56050DPU115R pinout, LD56050DPU115R application, or LD56050DPU115R equivalent, key selection criteria include VBIAS pin voltage compliance (≥VOUT + 1.4 V), thermal shutdown threshold (160 °C), output discharge MOSFET on-resistance (110 Ω), and stability with 1 µF X5R/X7R ceramic output capacitors.

Technical Context

The LD56050DPU115R uses an NMOS pass element whose gate is driven by a dedicated VBIAS pin - enabling ultra-low dropout even when VIN approaches VOUT. This architecture decouples control circuitry biasing from the main power path, reducing ground current to 27 µA at no load and maintaining regulation down to 0.8 V input.

It integrates foldback current limiting (ISC = 365–500 mA at VOUT = 0), thermal shutdown with 20 °C hysteresis, and logic-controlled enable (EN) with active discharge activation. The device requires only 1 µF input and 2.2 µF output ceramic capacitors for stable operation across –40 °C to +85 °C.

Key Specifications

Pinout & Package

LD56050DPU115R is housed in a DFN4 1.2 × 1.2 mm package with 0.8 mm pitch, featuring wettable flanks for automated optical inspection. The compact footprint saves >60% board area versus SOT-23 alternatives while supporting high thermal density designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-dropout LDO applications.

Compared with XC6210B115MR-G and RT9080AL-115GJ6F, the LD56050DPU115R uniquely combines VBIAS-enabled ultra-low dropout, integrated output discharge, and 27 µA quiescent current - making it the only choice for battery-powered systems demanding simultaneous low-noise, fast shutdown, and sub-1.3 V operational headroom.

Availability

LD56050DPU115R is available at Aetrix Electronics and suitable for mobile phones, tablets, and battery-powered imaging systems requiring stable component supply with guaranteed long-term manufacturability and full traceability.

Supply support for LD56050DPU115R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LD56050 belongs to ST's high-accuracy, ultra-low-IQ LDO portfolio targeting space- and power-constrained portable electronics - engineered specifically to replace legacy Pch-based regulators in next-generation mobile and wearable platforms.

FAQ

What is the minimum required VBIAS voltage for LD56050DPU115R at 1.15 V output?

The minimum VBIAS voltage is VOUT + 1.4 V, i.e., 2.55 V. This ensures sufficient gate overdrive for the NMOS pass transistor to maintain regulation at full 500 mA load. If VIN ≥ 2.55 V, VBIAS may be tied directly to VIN; otherwise, a separate bias rail or charge pump is required.

Can LD56050DPU115R operate with a 1 µF output capacitor?

Yes - the LD56050DPU115R is internally compensated and stable with any good-quality 1–22 µF ceramic capacitor (X5R/X7R dielectric). A 2.2 µF value is recommended for optimal transient response, but 1 µF meets minimum stability requirements per DS12441 Section 6.5.

How does the output discharge function behave during shutdown?

When EN is pulled low, the internal 110 Ω discharge MOSFET turns on, actively sinking current from VOUT to GND. This discharges the output capacitor to <100 mV within ~100 µs, preventing back-powering of upstream circuits and ensuring safe power-down sequencing in multi-rail systems.

What thermal derating applies above 25 °C ambient?

Using RthJA = 170 °C/W, maximum allowable power dissipation decreases linearly: PDMAX = (85 − TAMB)/170 W. At 60 °C ambient, PDMAX = 0.147 W - corresponding to ~130 mA at 1.15 V output with 1.5 V input (0.35 V dropout), requiring careful layout or forced airflow for higher loads.