STMicroelectronics LD59150PURY

Overview

LD59150PURY from STMicroelectronics is an AEC-Q100 qualified 1.5 A low-dropout linear regulator with dual supply inputs (VIN: 0.8–5.5 V, VBIAS: 2.7–5.5 V), adjustable output (0.8–3.6 V), ultra-low dropout (65 mV typ. at 1.5 A), and integrated Power Good and programmable soft-start functions. It serves as a post-regulator in automotive ADAS domain controllers and industrial FPGA power rails where high accuracy (±0.5% typ.), thermal robustness (−40 °C to +125 °C), and controlled power sequencing are critical.

For engineers reviewing the LD59150PURY datasheet, LD59150PURY pinout, LD59150PURY application, or LD59150PURY equivalent, key selection criteria include its NMOS pass transistor architecture enabling sub-100 mV dropout at full load, dual-rail biasing for efficiency in low-VIN systems, PG/EN sequencing capability, and wettable-flank DFN10 package for automated optical inspection in automotive-grade assembly.

Technical Context

The LD59150PURY employs an NMOS pass element with R_DS(on) optimized for minimal dropout-65 mV typical at 1.5 A-enabling stable regulation even when VIN approaches VOUT + 65 mV. Its dual-supply architecture separates input power path (VIN) from bias rail (VBIAS), allowing efficient operation down to 0.8 V input while maintaining full functionality via independent 2.7–5.5 V bias supply.

Internal circuitry includes a precision 0.8 V bandgap reference, feedback amplifier with ±0.5% output accuracy over temperature, open-drain Power Good comparator with 90% VOUT threshold and 3% hysteresis, and a constant-current soft-start generator (0.44 µA typ.) enabling monotonic ramp control via external CSS capacitor.

Key Specifications

Pinout & Package

LD59150PURY is housed in a 3 × 3 mm DFN10 package with wettable flanks for solder joint inspection, featuring an exposed thermal pad that must be connected to GND for optimal thermal performance (R_thJC = 8 °C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with XC6216D122MR-G and ADM7172ACPZ-R7, LD59150PURY uniquely combines AEC-Q100 qualification, dual-supply operation, sub-100 mV dropout at 1.5 A, and wettable-flank packaging-making it the only option qualified for thermally demanding, safety-aware automotive post-regulation where rail sequencing and manufacturability are mandatory.

Availability

LD59150PURY is available at Aetrix Electronics and suitable for automotive ADAS domain controllers, industrial FPGA power management, and telecom point-of-load regulation requiring stable component supply with full AEC-Q100 traceability and long-term lifecycle support.

Supply support for LD59150PURY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in automotive, industrial, and power management ICs, with broad portfolio coverage from microcontrollers to analog regulators and sensors.

LD59150PURY belongs to ST's high-reliability LDO family designed specifically for automotive and industrial post-regulation-emphasizing ultra-low dropout, precise output accuracy, and robust protection features for mission-critical power rails.

FAQ

What is the minimum input voltage required for 1.5 A output at 0.8 V?

The LD59150PURY achieves 1.5 A output at 0.8 V with VIN as low as 0.865 V, based on its 65 mV typical dropout voltage (0.8 V + 0.065 V). This is validated across −40 °C to +125 °C ambient and requires VBIAS ≥ 2.7 V. Operation below this VIN risks dropout and regulation loss.

How is Power Good used in multi-rail sequencing?

PG is an open-drain output that goes high-impedance when VOUT reaches 90% of target and pulls low otherwise. When paired with EN of downstream regulators (e.g., via pull-up to next rail), it creates cascaded startup: Rail A enables Rail B only after PG asserts, enforcing strict monotonic sequencing required in FPGA and SoC power trees.

Can the LD59150PURY operate without connecting VBIAS?

No. VBIAS must be connected to a 2.7–5.5 V supply; leaving it unconnected violates absolute maximum ratings and disables internal bias circuitry. The device will not regulate-even if VIN is present-because control logic, reference, and error amplifier require VBIAS to function.

What capacitor values are recommended for stable operation?

Stability requires ≥2.2 µF ceramic output capacitor (X5R/X7R, low ESR), ≥10 µF input capacitor, 0.1 µF VBIAS bypass, and 1 nF soft-start capacitor (CSS). For noise-sensitive applications, increasing COUT to 22–47 µF further reduces output ripple without compromising phase margin.