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NXP Semiconductors LD6805K/12P,115
- Part No.:
- LD6805K/12P,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 4-UDFN Exposed Pad
- Datasheet:
-
LD6805K/12P,115.pdf
- Description:
- IC REG LIN 1.2V 150MA DFN1010C-4
- Quantity:
- Payment:
- Shipping:
Inventory:1,265
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Product details
Overview
LD6805K/12P,115 from NXP Semiconductors is a 1.2 V fixed-output, 150 mA low-dropout regulator (LDO) with ultra-high PSRR (75 dB at 1 kHz), 250 mV dropout at full load, and auto-discharge functionality enabled via integrated pull-down transistor. It operates from 2.3 V to 5.5 V input and targets power-sensitive portable electronics requiring clean, stable low-voltage rails.
For engineers reviewing the LD6805K/12P,115 datasheet, LD6805K/12P,115 pinout, LD6805K/12P,115 application, or LD6805K/12P,115 equivalent, key selection criteria include its 1.2 V output accuracy (±0.5% at +25°C), 40 µV RMS output noise, 150 µs startup time, and DFN1010C-4 (1 × 1 mm) thermal-enhanced package for space-constrained designs.
Technical Context
The LD6805K/12P,115 integrates a precision voltage reference, error amplifier, and PMOS pass transistor in monolithic silicon. Its enable input (EN, active HIGH) controls regulation and activates the internal 100 Ω pull-down switch during shutdown to discharge the output capacitor - critical for system-level power sequencing and leakage control.
This LDO uses a stable internal compensation scheme compatible with 1.0 µF X7R ceramic output capacitors (ESR 5–500 mΩ). Its high PSRR stems from optimized internal feedback loop gain and rejection architecture, maintaining >60 dB suppression up to 100 kHz, making it suitable for noise-sensitive analog and RF supply domains.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.2 V ±0.5% at +25°C; supports precision core logic and low-voltage I/O rails |
| Max Output Current | 150 mA continuous; sufficient for single-core microcontrollers or sensor interfaces |
| Dropout Voltage | 250 mV at 150 mA; enables operation down to 1.45 V input for battery-powered systems |
| PSRR | 75 dB at 1 kHz; suppresses switching noise from upstream DC-DC converters |
| Output Noise | 40 µV RMS (10 Hz–100 kHz); minimizes jitter in clocked circuits and ADC references |
| Quiescent Current | 0.1 µA typical in shutdown; reduces standby power in always-on subsystems |
| Startup Time | 150 µs to 95% of 1.2 V; supports fast wake-up in duty-cycled applications |
Pinout & Package
LD6805K/12P,115 is housed in a DFN1010C-4 (SOT1194-1) plastic package measuring 1.0 × 1.0 × 0.55 mm with thermal-enhanced exposed tab (GND-connected). The 4-pin layout supports minimal PCB footprint and efficient heat dissipation in thin-profile portable devices.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: OUT | Regulated output voltage node | Delivers stable 1.2 V; requires 1.0 µF X7R ceramic capacitor for stability and controlled shutdown discharge |
| 2: GND | Supply ground reference | Common return path; TAB is internally connected to GND and must be soldered to PCB ground plane for optimal thermal performance |
| 3: EN | Enable control input | Active-HIGH logic interface (VIH ≥ 1.1 V); asserts auto-discharge when pulled LOW |
| 4: IN | Input voltage supply | Accepts 2.3–5.5 V; designed for direct connection to battery or intermediate DC-DC stage |
Key Features
| Feature | Design Value |
|---|---|
| Auto-discharge function | Integrated 100 Ω pull-down transistor discharges output capacitor during disable, preventing floating voltage and enabling safe power sequencing |
| Ultra-low output noise | 40 µV RMS noise (10 Hz–100 kHz) ensures minimal interference in precision analog signal chains and RF front-ends |
| High PSRR architecture | 75 dB rejection at 1 kHz and >60 dB up to 100 kHz maintains clean supply under noisy input conditions |
| Thermal-enhanced DFN package | DFN1010C-4 (1 × 1 mm) with exposed GND tab achieves 250 K/W junction-to-ambient thermal resistance on standard 2-layer PCB |
| Robust ESD protection | 6 kV HBM ESD rating per IEC 61340-3-1 enables reliable handling and assembly in high-volume manufacturing |
Applications
| Smartphone Application Processor Core Supply | Digital Still Camera Image Sensor Bias |
|---|---|
Use Scenario: Powers ARM Cortex-A series CPU cores requiring tightly regulated 1.2 V with fast transient response and low noise. IC Role / Device Role / Timing Role: Primary low-noise post-regulator delivering clean bias to processor VDD_CORE rail. Use Value: 75 dB PSRR rejects ripple from main PMIC buck converters; 150 µs startup aligns with SoC wake-up timing requirements. | Use Scenario: Supplies bias voltage to CMOS image sensor analog front-end (AFE) and ADC reference circuitry. IC Role / Device Role / Timing Role: Low-noise LDO providing stable 1.2 V reference for pixel readout and analog signal conditioning. Use Value: 40 µV RMS noise prevents quantization errors in 12-bit+ image data; auto-discharge ensures sensor reset integrity between frames. |
| Portable Media Player Audio Codec Supply | Personal Navigation Device GPS Baseband IC Supply |
Use Scenario: Powers stereo audio codec's analog supply (AVDD) in battery-operated MP3 players. IC Role / Device Role / Timing Role: Dedicated low-noise LDO isolating sensitive audio circuitry from digital switching noise. Use Value: 250 mV dropout extends battery life by enabling operation down to 1.45 V input; 0.1 µA shutdown current preserves battery during pause mode. | Use Scenario: Supplies 1.2 V to GPS baseband processor and RF synthesizer blocks in handheld navigation units. IC Role / Device Role / Timing Role: Precision LDO delivering stable supply to timing-critical GNSS correlation engines. Use Value: High PSRR suppresses coupling from cellular/Wi-Fi coexistence interference; 1.2 V accuracy ensures consistent oscillator frequency calibration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS7A0512PDBVR | 1.2 V, 200 mA, 170 mV dropout, 45 dB PSRR @ 1 kHz, SOT-23-5 package | Larger footprint, lower PSRR, no auto-discharge | Choose when higher current or simpler enable logic is prioritized over noise rejection and output discharge control |
| MCP1700T-1202E/TT | 1.2 V, 250 mA, 600 mV dropout, 55 dB PSRR @ 1 kHz, SOT-23-3 package | No enable pin, no auto-discharge, higher dropout limits low-VIN use | Choose for cost-sensitive, non-sequenced applications where 250 mA output suffices and board space allows larger dropout margin |
Compared with TPS7A0512PDBVR and MCP1700T-1202E/TT, LD6805K/12P,115 delivers superior noise immunity (75 dB vs ≤55 dB PSRR), tighter output accuracy (±0.5% vs ±2%), and unique auto-discharge capability - making it optimal for compact, noise-sensitive, and power-sequenced portable systems.
Availability
LD6805K/12P,115 is available at Aetrix Electronics and suitable for smartphone power management, portable media player audio subsystems, digital camera sensor biasing, and GPS baseband IC supply requiring stable component supply, tight voltage tolerance, and low-noise operation.
Supply support for LD6805K/12P,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer applications.
The LD6805 series belongs to NXP's high-PSRR LDO portfolio, engineered specifically for miniaturized portable electronics demanding ultra-clean, low-voltage power rails with fast enable/disable control and thermal efficiency in sub-1 mm² packages.
FAQ
What is the output voltage tolerance of LD6805K/12P,115 across temperature?
The LD6805K/12P,115 guarantees ±0.5% output voltage accuracy at +25°C and ±3% over the full operating range of −40°C to +85°C. This specification is verified per Table 8 in the NXP product data sheet Rev. 2 (2012), ensuring stable 1.2 V delivery for precision logic and analog circuits without external trimming. LD6805K/12P,115 maintains this tolerance under 1 mA load and nominal input conditions.
Does LD6805K/12P,115 require an external output capacitor, and what type is recommended?
Yes, LD6805K/12P,115 requires a minimum 0.7 µF external ceramic output capacitor for stability, with 1.0 µF X7R recommended per Table 9 and Section 10.1. The capacitor must have ESR between 5 mΩ and 500 mΩ. Using this value ensures proper phase margin, controlled startup/shutdown behavior, and compliance with the specified 150 µs startup and 300 µs shutdown times. LD6805K/12P,115 is not stable with tantalum or electrolytic capacitors due to ESR mismatch.
How does the auto-discharge function work in LD6805K/12P,115?
When the EN pin of LD6805K/12P,115 is driven LOW, the device enters shutdown mode and activates an internal 100 Ω pull-down transistor between OUT and GND. This provides a low-ohmic discharge path for the output capacitor, rapidly bringing VOUT to near-zero volts. This feature is confirmed in Sections 1.1 and 1.2 of the datasheet and distinguishes LD6805K/12P,115 from the /xxH variant, which leaves OUT in high-impedance state. LD6805K/12P,115 thus enables safe power sequencing in multi-rail systems.
What is the thermal resistance (Rth(j-a)) of LD6805K/12P,115, and how is it achieved?
The typical junction-to-ambient thermal resistance of LD6805K/12P,115 is 250 K/W under standard test conditions (2-layer PCB, Tamb = 25°C), as specified in Table 7. This value assumes the exposed GND tab is soldered to a solid copper ground plane using the recommended footprint in Figure 9. Thermal performance degrades significantly if the tab is left unconnected or covered with solder mask. LD6805K/12P,115 relies on this tab for primary heat conduction, not just the four perimeter pins.
Is LD6805K/12P,115 RoHS compliant and halogen-free?
Yes, LD6805K/12P,115 is Pb-free, RoHS compliant, and free of halogen and antimony per the "dark green compliant" designation in Section 1.2. It meets the EU RoHS Directive 2011/65/EU and satisfies JEDEC J-STD-020 moisture sensitivity level (MSL) requirements for surface-mount reflow. The DFN1010C-4 package uses environmentally compliant molding compound and termination finish, as verified in the NXP quality documentation NX2-00001. LD6805K/12P,115 carries full compliance documentation through NXP's official channels.
LD6805K/12P,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 4-UDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.2V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 35 µA
- Current - Supply (Max):
- 150 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Transient Voltage
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1010C-4
LD6805K/12P,115 FAQ
1.How can I place an order for LD6805K/12P,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6805K/12P,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6805K/12P,115 reliable?
The price and inventory of LD6805K/12P,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6805K/12P,115 is usually 5 days.
3.What payment methods are accepted for LD6805K/12P,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6805K/12P,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LD6805K/12P,115?
LD6805K/12P,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6805K/12P,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6805K/12P,115?
For technical support, including LD6805K/12P,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6805K/12P,115 requirements.
6.How does Aetrix verify that LD6805K/12P,115 is sourced from the original manufacturer or authorized distributors?
All LD6805K/12P,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6805K/12P,115 meets industry standards.
7.What is the process for return or replacement of LD6805K/12P,115?
All LD6805K/12P,115 units undergo pre-shipment inspection (PSI). If there is an issue with LD6805K/12P,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6805K/12P,115 part is unused and in its original packaging.
Return procedure for LD6805K/12P,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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