NXP Semiconductors LD6805K/13H,115

Overview

LD6805K/13H from NXP Semiconductors is a fixed-output 1.3 V, 150 mA low-dropout regulator (LDO) with ultra-high PSRR (75 dB at 1 kHz), 250 mV dropout at full load, and ultra-small DFN1010C-4 (1 × 1 × 0.55 mm) package - designed for power-sensitive portable applications including smartphone baseband ICs and camera sensor rails.

For engineers reviewing the LD6805K/13H datasheet, LD6805K/13H pinout, LD6805K/13H application, or LD6805K/13H equivalent, key selection criteria include its high-ohmic disable state (3-state output), 40 µV_RMS output noise (10 Hz–100 kHz), 0.1 µA shutdown current, thermal resistance of 250 K/W, and compatibility with 1 µF X7R ceramic output capacitors.

Technical Context

The LD6805K/13H implements a CMOS-based LDO architecture with internal voltage reference, error amplifier, and PMOS pass transistor - enabling stable regulation across 2.3 V to 5.5 V input while maintaining tight output accuracy (±0.5% at +25 °C). Its enable input (active HIGH) controls a dedicated shutdown circuit that places the OUT pin in high-impedance state without external pull-down.

Unlike the /xxP variant, the LD6805K/13H omits the internal pull-down transistor, delivering true 3-state behavior during disable - critical for bus isolation and multi-rail sequencing in compact mobile SoC power domains. PSRR performance remains consistent across load (50 mA typical) and frequency (−75 dB @ 1 kHz), supported by internal compensation optimized for 1 µF output capacitance.

Key Specifications

Pinout & Package

LD6805K/13H uses the DFN1010C-4 (SOT1194-1) thermally enhanced plastic package: 1 × 1 × 0.55 mm body with exposed thermal pad (TAB) on underside, rated R_th(j-a) = 250 K/W on standard 2-layer PCB.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with XC6210B132MR-G and RT9013-13GB, the LD6805K/13H uniquely combines true 3-state disable, industry-leading 75 dB PSRR, and smallest-in-class 1 × 1 mm footprint - making it optimal for space-constrained, multi-rail portable designs where rail isolation and noise rejection are critical.

Availability

LD6805K/13H is available at Aetrix Electronics and suitable for smartphone baseband power, digital camera sensor rails, portable media player audio codecs, wearable health sensor hubs, and other portable electronics requiring stable component supply with guaranteed long-term availability.

Supply support for LD6805K/13H includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets.

The LD6805 series belongs to NXP's precision analog power management portfolio, engineered specifically for miniaturized portable electronics demanding ultra-low noise, high PSRR, and minimal footprint - with emphasis on smartphone, camera, and wearable subsystems.

FAQ

What is the output voltage tolerance of the LD6805K/13H over temperature?

The LD6805K/13H maintains ±0.5% output voltage accuracy at +25 °C and ±4% over the full operating range of −40 °C to +85 °C ambient temperature. This specification is verified per Table 8 in the official NXP datasheet Rev. 2 (2012), ensuring reliable regulation for precision analog loads like camera sensor AFEs and audio DACs without external trimming.

Does the LD6805K/13H require an external pull-down resistor on the EN pin?

No, the LD6805K/13H does not require an external pull-down resistor on the EN pin. Its enable input has defined logic thresholds (V_IL ≤ 0.4 V, V_IH ≥ 1.1 V) and internal biasing - allowing direct connection to GPIOs or open-drain controllers without external components. The LD6805K/13H datasheet confirms this in Section 6 (Recommended Operating Conditions).

Can the LD6805K/13H be used with a 0.7 µF output capacitor?

Yes, the LD6805K/13H is stable with a minimum 0.7 µF output capacitor, as specified in Table 9 and Section 10.1 of the datasheet. However, the recommended value is 1.0 µF X7R ceramic (±30% tolerance) for optimal transient response and PSRR performance - especially under dynamic load conditions common in mobile processor cores.

What is the thermal resistance (R_th(j-a)) of the LD6805K/13H in standard layout?

The LD6805K/13H has a typical junction-to-ambient thermal resistance of 250 K/W when mounted on a standard two-layer PCB with adequate copper pour connected to the exposed thermal pad (TAB). This value assumes solid GND connections to all pins and is documented in Table 7 of the NXP LD6805_SER datasheet Rev. 2.

How does the LD6805K/13H behave when disabled?

When disabled (EN pin held ≤ 0.4 V), the LD6805K/13H places the OUT pin in a high-impedance (3-state) condition - neither sourcing nor sinking current. This behavior is explicitly differentiated from the /xxP variant and confirmed in Section 1.1 and Figure 3 of the LD6805_SER datasheet, enabling safe rail isolation in multi-voltage domain systems.