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NXP Semiconductors LD6805K/13P,115
- Part No.:
- LD6805K/13P,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 4-UDFN Exposed Pad
- Datasheet:
-
LD6805K/13P,115.pdf
- Description:
- IC REG LIN 1.3V 150MA DFN1010C-4
- Quantity:
- Payment:
- Shipping:
Inventory:60,000
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Product details
Overview
LD6805K/13P,115 from NXP Semiconductors is a 1.3 V fixed-output, 150 mA low-dropout (LDO) regulator in a 1 × 1 mm DFN package, featuring 75 dB PSRR at 1 kHz, 250 mV dropout at full load, and auto-discharge functionality via integrated pull-down transistor. It operates from 2.3 V to 5.5 V input and targets power-sensitive portable electronics requiring stable low-voltage rails.
For engineers reviewing the LD6805K/13P,115 datasheet, LD6805K/13P,115 pinout, LD6805K/13P,115 application, or LD6805K/13P,115 equivalent, this page delivers verified electrical specs, thermal behavior, enable timing, noise performance, and real-world use context - all aligned with NXP's Rev. 2 (25 June 2012) product data sheet.
Technical Context
The LD6805K/13P,115 implements a PMOS pass transistor architecture enabling ultra-low dropout and high PSRR. Its internal voltage reference and error amplifier deliver ±0.5% output accuracy at +25 °C and ±3% over −40 °C to +85 °C ambient.
It integrates an active HIGH enable input (VIH = 1.1 V min), 150 µs startup time, and 300 µs shutdown time with auto-discharge (Rpd = 100 Ω typical). The device uses monolithic silicon technology and supports 0.7–1.0 µF X7R ceramic output capacitors with ESR between 5 mΩ and 500 mΩ.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.3 V ±0.5% at +25 °C; ±3% over full temperature range - ensures stable core logic supply for low-voltage microcontrollers. |
| Dropout Voltage | 250 mV at 150 mA - enables operation with minimal headroom (e.g., 1.55 V input for 1.3 V output), reducing power loss and heat generation. |
| PSRR | 75 dB at 1 kHz - suppresses switching noise from upstream DC-DC converters, critical for analog sensor or RF subsystems. |
| Output Noise | 40 µV RMS (10 Hz–100 kHz) - low enough for noise-sensitive analog circuits like ADC references or audio bias rails. |
| Quiescent Current | 0.1 µA typical in shutdown mode - extends battery life in always-on standby applications such as IoT wake-up controllers. |
| Enable Threshold | VIL ≤ 0.4 V, VIH ≥ 1.1 V - compatible with 1.8 V and 3.3 V GPIOs without level-shifting. |
| Thermal Resistance | Rth(j-a) = 250 K/W (typical, two-layer PCB) - requires solid GND pad connection and thermal vias for sustained 150 mA operation at +85 °C ambient. |
Pinout & Package
LD6805K/13P,115 is housed in a DFN1010C-4 (SOT1194-1) plastic package: 1 × 1 × 0.55 mm body size with exposed thermal pad (TAB) on underside connected internally to GND. Recommended PCB layout includes direct TAB-to-GND copper connection for optimal thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output voltage node | Delivers 1.3 V to load; requires 0.7–1.0 µF X7R ceramic capacitor with 5–500 mΩ ESR for stability and controlled shutdown time. |
| 2 - GND | Supply ground reference | Primary return path for load current and internal circuitry; must be connected to system GND plane with low-inductance routing. |
| 3 - EN | Active-HIGH enable control input | Drives internal pass transistor; asserts regulation when ≥1.1 V applied; pulls output low via 100 Ω pull-down when disabled (auto-discharge). |
| 4 - IN | Input voltage supply node | Accepts 2.3–5.5 V; requires local 1 µF ceramic decoupling near pin to minimize input ripple and transient impedance. |
Key Features
| Feature | Design Value |
|---|---|
| Auto-discharge function | Integrated 100 Ω pull-down transistor actively discharges output capacitance during disable, preventing floating or unintended biasing of downstream circuitry. |
| Ultra-high PSRR | 75 dB at 1 kHz enables clean power delivery to noise-sensitive analog blocks even when sharing input rail with noisy digital or switching supplies. |
| Low-noise regulation | 40 µV RMS output noise (10 Hz–100 kHz) meets requirements for precision analog front-ends and low-jitter clock buffers. |
| Miniaturized thermal package | DFN1010C-4 (1 × 1 mm) with exposed GND pad supports >150 mA continuous output in space-constrained mobile designs without external heatsinking. |
| ESD robustness | 6 kV HBM rating allows safe handling and assembly in standard production environments without special ESD controls beyond IPC-610 Class 2. |
Applications
| Smartphone Baseband Core Supply | Digital Still Camera Sensor Bias Rail |
|---|---|
Use Scenario: Powers 1.3 V I/O or core logic of baseband processors during active and low-power modes in smartphones. IC Role / Device Role / Timing Role: Primary LDO delivering regulated, low-noise 1.3 V supply with fast enable/disable sequencing synchronized to processor sleep states. Use Value: Auto-discharge prevents residual charge on processor I/O lines during deep-sleep, eliminating leakage paths and ensuring reliable wake-up. |
Use Scenario: Supplies bias voltage to CMOS image sensor analog front-end in compact digital cameras. IC Role / Device Role / Timing Role: Low-noise, high-PSRR LDO isolating sensor analog section from noisy digital domain and DC-DC converter ripple. Use Value: 40 µV RMS noise and 75 dB PSRR preserve signal integrity and dynamic range in high-resolution image capture. |
| Portable Media Player Audio Codec | Personal Navigation Device GPS Front-End |
Use Scenario: Provides clean 1.3 V supply to stereo audio codec ICs in battery-powered media players. IC Role / Device Role / Timing Role: Secondary LDO generating low-noise analog supply independent of main system rail, with fast startup (<150 µs) for responsive playback. Use Value: Ultra-low dropout (250 mV) extends usable battery voltage range, increasing playback time per charge. |
Use Scenario: Delivers stable 1.3 V to GPS RF front-end and baseband ICs in handheld navigation devices. IC Role / Device Role / Timing Role: High-PSRR LDO rejecting switching noise from PMU and display backlight drivers to maintain GPS sensitivity and acquisition speed. Use Value: 250 K/W thermal resistance and 1 × 1 mm footprint enable integration into thermally constrained GPS modules without derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6206P132MR-G | 1.3 V fixed, 150 mA, SOT-23-5 package (2.9 × 1.6 mm); no auto-discharge; PSRR = 65 dB @ 1 kHz; higher quiescent current (1 µA typ. in shutdown) | Lacks pull-down discharge; larger footprint; lower PSRR limits suitability in high-noise RF/analog systems | Choose if board space allows SOT-23-5 and auto-discharge is not required; verify PSRR margin against system noise floor. |
| Richtek RT9013-13GB | 1.3 V fixed, 300 mA, DFN-4 (1 × 1 mm); no auto-discharge; PSRR = 70 dB @ 1 kHz; 0.5 µA shutdown current | Higher current capability but no discharge path; slightly lower PSRR and noise (50 µV RMS) than LD6805K/13P,115 | Select when higher load current headroom is needed and output discharge is managed externally via MOSFET or resistor network. |
Compared with XC6206P132MR-G and RT9013-13GB, LD6805K/13P,115 uniquely combines 1 × 1 mm footprint, 75 dB PSRR, 40 µV noise, and integrated auto-discharge - making it optimal for miniaturized, noise-critical portable systems where output rail control during disable is mandatory.
Availability
LD6805K/13P,115 is available at Aetrix Electronics and suitable for smartphone baseband supplies, digital camera sensor bias rails, portable media player audio codecs, and personal navigation device GPS front-ends requiring stable component supply with guaranteed long-term sourcing.
Supply support for LD6805K/13P,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets.
The LD6805 series belongs to NXP's high-PSRR, miniaturized LDO portfolio designed specifically for portable electronics demanding ultra-low noise, fast transient response, and space-efficient power management in battery-constrained environments.
FAQ
What is the exact output voltage tolerance of LD6805K/13P,115 across temperature?
The LD6805K/13P,115 delivers 1.3 V with ±0.5% tolerance at +25 °C and ±3% over the full operating range of −40 °C to +85 °C ambient temperature. This specification is confirmed in Table 8 of the NXP product data sheet Rev. 2 (25 June 2012), under "ΔVO output voltage variation" for VOUT < 1.8 V.
Does LD6805K/13P,115 require an input capacitor, and what value is recommended?
Yes, LD6805K/13P,115 requires a local 1 µF ceramic input capacitor placed close to the IN pin to stabilize the input rail and suppress high-frequency transients. While not strictly mandatory for stability, omission risks degraded PSRR and potential oscillation under dynamic load conditions per Section 10.1 of the datasheet.
How does the auto-discharge function of LD6805K/13P,115 operate during disable?
When the EN pin is driven LOW (≤0.4 V), LD6805K/13P,115 activates an internal 100 Ω pull-down transistor between OUT and GND, actively discharging external output capacitance. This ensures rapid, controlled voltage decay - critical for preventing latch-up or false triggering in downstream logic during power sequencing.
What is the maximum allowable input voltage for LD6805K/13P,115, and is it absolute maximum or recommended?
The absolute maximum input voltage for LD6805K/13P,115 is +6.0 V for 4 ms transients (Table 5), while the recommended operating range is 2.3 V to 5.5 V (Table 6). Continuous operation above 5.5 V violates recommended conditions and risks reliability degradation or permanent damage per NXP's limiting values table.
Can LD6805K/13P,115 be used with tantalum output capacitors?
No - LD6805K/13P,115 is specified for use with ceramic capacitors only (X7R dielectric, 0.7–1.0 µF, 5–500 mΩ ESR). Tantalum capacitors exhibit higher ESR and potential instability risks; using them may cause oscillation or failure to meet startup/shutdown timing specs per Section 10.1 and Table 9 of the datasheet.
LD6805K/13P,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 4-UDFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.3V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 35 µA
- Current - Supply (Max):
- 150 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Transient Voltage
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1010C-4
LD6805K/13P,115 FAQ
1.How can I place an order for LD6805K/13P,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6805K/13P,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6805K/13P,115 reliable?
The price and inventory of LD6805K/13P,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6805K/13P,115 is usually 5 days.
3.What payment methods are accepted for LD6805K/13P,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6805K/13P,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LD6805K/13P,115?
LD6805K/13P,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6805K/13P,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6805K/13P,115?
For technical support, including LD6805K/13P,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6805K/13P,115 requirements.
6.How does Aetrix verify that LD6805K/13P,115 is sourced from the original manufacturer or authorized distributors?
All LD6805K/13P,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6805K/13P,115 meets industry standards.
7.What is the process for return or replacement of LD6805K/13P,115?
All LD6805K/13P,115 units undergo pre-shipment inspection (PSI). If there is an issue with LD6805K/13P,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6805K/13P,115 part is unused and in its original packaging.
Return procedure for LD6805K/13P,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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