NXP Semiconductors LD6805K/14H,115
- Part No.:
- LD6805K/14H,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 4-UDFN Exposed Pad
- Datasheet:
-
LD6805K/14H,115.pdf
- Description:
- IC REG LIN 1.4V 150MA DFN1010C-4
- Quantity:
- Payment:

- Shipping:

Inventory:60,000
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Product details
Overview
LD6805K/14H,115 from NXP Semiconductors is a 1.4 V fixed-output, 150 mA low-dropout (LDO) regulator in a 1 × 1 mm DFN package, featuring 75 dB PSRR at 1 kHz, 250 mV dropout at full load, and high-ohmic (3-state) output during disable. It operates from 2.3 V to 5.5 V input and delivers ultra-low 40 µVRMS output noise for powering noise-sensitive analog circuitry in portable electronics.
For engineers reviewing the LD6805K/14H,115 datasheet, LD6805K/14H,115 pinout, LD6805K/14H,115 application, or LD6805K/14H,115 equivalent, this page provides verified specifications, thermal performance data, enable timing (150 µs startup), shutdown behavior (high-ohmic state), and real-world design guidance for mobile power rail stabilization.
Technical Context
The LD6805K/14H,115 integrates a precision voltage reference, error amplifier, and PMOS pass transistor in monolithic silicon. Its high-ohmic disable mode isolates the output without sinking current, preserving battery charge in standby states of handheld devices.
PSRR is maintained above 70 dB from 10 Hz to 10 kHz via internal compensation and layout-optimized feedback path. The device requires only a 1 µF X7R ceramic output capacitor (ESR 5–500 mΩ) for stability across −40 °C to +85 °C ambient operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.4 V ±2% over temperature; enables direct replacement of 1.4 V logic rails without external resistors. |
| Max Output Current | 150 mA continuous; supports power delivery to multiple low-power peripherals (e.g., sensors, RF front-ends). |
| Dropout Voltage | 250 mV at 150 mA; allows regulation from 1.65 V input, extending battery life in single-cell Li-ion or Li-poly systems. |
| PSRR | 75 dB at 1 kHz; suppresses switching noise from adjacent DC-DC converters feeding shared input rails. |
| Quiescent Current | 0.1 µA typical in shutdown; reduces leakage current in always-on subsystems like RTC or wake-up controllers. |
| Output Noise | 40 µVRMS (10 Hz–100 kHz); meets stringent noise requirements for ADC references and RF synthesizer VCO supplies. |
| Enable Threshold | VIH = 1.1 V min; compatible with 1.8 V GPIOs without level-shifting; VIL ≤ 0.4 V ensures robust noise immunity. |
Pinout & Package
LD6805K/14H,115 uses the DFN1010C-4 (SOT1194-1) package: 1 × 1 × 0.55 mm body with exposed thermal pad (TAB) on underside, rated for 250 K/W junction-to-ambient thermal resistance when properly soldered to ground plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output voltage node | Delivers stable 1.4 V; requires ≥0.7 µF ceramic capacitor with ESR 5–500 mΩ for loop stability. |
| 2 - GND | Power and reference ground | Primary return path; TAB must be connected to PCB ground plane for optimal thermal and EMI performance. |
| 3 - EN | Active-HIGH enable control | Pulls up to VIN or 1.1–5.5 V to activate regulator; <0.4 V disables with high-ohmic output state. |
| 4 - IN | Unregulated input supply | Accepts 2.3–5.5 V; requires local 1 µF decoupling capacitor near pin to minimize input impedance. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-high PSRR | 75 dB at 1 kHz enables clean power delivery in noisy mixed-signal environments (e.g., smartphone baseband + RF sections). |
| High-ohmic disable | Output floats to high-impedance state when EN = LOW, preventing backfeed into powered-down subsystems. |
| Low-noise regulation | 40 µVRMS noise floor supports high-resolution analog signal chains without additional filtering. |
| Miniature footprint | 1 × 1 mm DFN package saves >60% board area vs. SOT-23 alternatives-critical for ultra-thin mobile designs. |
| Robust ESD protection | 6 kV HBM rating eliminates need for external TVS diodes in handheld product ESD test plans. |
Applications
| Smartphone Baseband Power | Digital Camera Sensor Bias |
|---|---|
|
Use Scenario: Supplies 1.4 V bias to CMOS image sensor analog front-end and column ADC drivers. IC Role / Device Role / Timing Role: Low-noise LDO providing isolated, ripple-free voltage for pixel readout circuits. Use Value: 40 µVRMS noise prevents fixed-pattern noise and quantization errors in 12-bit+ imaging pipelines. |
Use Scenario: Powers RF transceiver's LNA and mixer bias rails in LTE/Wi-Fi combo modules. IC Role / Device Role / Timing Role: High-PSRR post-regulator cleaning switched-mode supply ripple before sensitive RF stages. Use Value: 75 dB PSRR attenuates 1 MHz–10 MHz DC-DC switching artifacts, improving receiver sensitivity by ≥3 dB. |
| Portable Media Player Audio Codec | Wearable Health Monitor Analog Front-End |
|
Use Scenario: Delivers 1.4 V to stereo DAC and headphone amplifier in battery-powered audio players. IC Role / Device Role / Timing Role: Low-quiescent, fast-startup regulator enabling instant audio playback from sleep mode. Use Value: 150 µs startup time and 0.1 µA shutdown current extend playback duration between charges. |
Use Scenario: Powers ECG/PPG analog signal conditioning chain in compact wearable patches. IC Role / Device Role / Timing Role: Miniaturized, thermally efficient LDO fitting under curved flex PCBs with limited copper area. Use Value: 1 × 1 mm DFN footprint and 250 K/W Rth(j-a) allow reliable operation in sealed, passive-cooled enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6219B142MR-G | Same 1.4 V output, 150 mA rating, but 65 dB PSRR at 1 kHz and 50 µVRMS noise; SOT-25 package (2.9 × 2.8 mm). | Larger footprint; lower PSRR limits use in RF-critical paths; suitable for cost-sensitive consumer audio. | Select when board space permits larger package and PSRR >70 dB is not required. |
| Richtek RT9013-14GB | 1.4 V, 300 mA output, 70 dB PSRR, 45 µVRMS noise; WDFN-6 package (1.2 × 1.2 mm) with thermal pad. | Higher current capability but larger size and no high-ohmic disable-output actively sinks during shutdown. | Choose when higher load margin is needed and auto-discharge function is acceptable. |
Compared with XC6219B142MR-G and RT9013-14GB, the LD6805K/14H,115 uniquely combines 1.4 V precision, 75 dB PSRR, 40 µVRMS noise, and high-ohmic disable in the smallest 1 × 1 mm footprint-making it optimal for space-constrained, noise-sensitive portable power rails.
Availability
LD6805K/14H,115 is available at Aetrix Electronics and suitable for smartphone baseband power, portable media player audio codecs, and wearable health monitor analog front-ends requiring stable component supply with guaranteed long-term availability.
Supply support for LD6805K/14H,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and mobile applications.
The LD6805 series belongs to NXP's high-performance analog power management portfolio, designed specifically for miniaturized portable electronics demanding ultra-low noise, high PSRR, and minimal board footprint.
FAQ
What is the exact output voltage tolerance of the LD6805K/14H,115 across temperature?
The LD6805K/14H,115 delivers a nominal 1.4 V output with ±2% tolerance over the full operating range of −40 °C to +85 °C ambient temperature. At +25 °C, the variation tightens to ±0.5%, ensuring precise voltage alignment for 1.4 V logic and analog interfaces. This specification is guaranteed per Table 8 in the official NXP datasheet Rev. 2 (2012).
Does the LD6805K/14H,115 require an input capacitor, and if so, what value is recommended?
Yes, the LD6805K/14H,115 requires a local 1 µF ceramic input capacitor placed as close as possible to the IN pin to suppress high-frequency noise and stabilize the input source. While not strictly mandatory for basic functionality, omitting it risks instability under transient load conditions and degrades PSRR performance-especially critical when fed from switching regulators.
How does the high-ohmic disable mode of the LD6805K/14H,115 differ from auto-discharge (P-version) behavior?
When disabled (EN < 0.4 V), the LD6805K/14H,115 places the OUT pin in a high-impedance (3-state) condition-no current flows into or out of the pin. In contrast, LD6805K/xxP variants integrate a pull-down transistor that actively discharges the output capacitance. This makes the LD6805K/14H,115 ideal for systems where output isolation-not rapid discharge-is required during sleep.
Can the LD6805K/14H,115 be used with ceramic capacitors having ESR below 5 mΩ?
No. The LD6805K/14H,115 requires an output capacitor with ESR between 5 mΩ and 500 mΩ for guaranteed stability, as specified in Table 9. Ultra-low-ESR ceramics (<5 mΩ) may cause oscillation or overshoot during load transients. Use X7R dielectric types with 1 µF nominal value and ±30% tolerance to meet both ESR and temperature stability requirements.
What is the maximum allowable junction temperature for continuous operation of the LD6805K/14H,115?
The LD6805K/14H,115 has a maximum junction temperature (Tj) rating of +125 °C. To maintain reliability, thermal design must ensure Tj stays within this limit under worst-case conditions (e.g., 150 mA load, +85 °C ambient). With its 250 K/W junction-to-ambient thermal resistance, achieving this requires solid GND plane connection to the exposed TAB and adequate PCB copper area.
LD6805K/14H,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 4-UDFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.4V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 35 µA
- Current - Supply (Max):
- 150 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Transient Voltage
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1010C-4
LD6805K/14H,115 FAQ
1.How can I place an order for LD6805K/14H,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6805K/14H,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6805K/14H,115 reliable?
The price and inventory of LD6805K/14H,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6805K/14H,115 is usually 5 days.
3.What payment methods are accepted for LD6805K/14H,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6805K/14H,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LD6805K/14H,115?
LD6805K/14H,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6805K/14H,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6805K/14H,115?
For technical support, including LD6805K/14H,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6805K/14H,115 requirements.
6.How does Aetrix verify that LD6805K/14H,115 is sourced from the original manufacturer or authorized distributors?
All LD6805K/14H,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6805K/14H,115 meets industry standards.
7.What is the process for return or replacement of LD6805K/14H,115?
All LD6805K/14H,115 units undergo pre-shipment inspection (PSI). If there is an issue with LD6805K/14H,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6805K/14H,115 part is unused and in its original packaging.
Return procedure for LD6805K/14H,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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