NXP Semiconductors LD6805K/20H,115
- Part No.:
- LD6805K/20H,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 4-UDFN Exposed Pad
- Datasheet:
-
LD6805K/20H,115.pdf
- Description:
- IC REG LIN 2V 150MA DFN1010C-4
- Quantity:
- Payment:

- Shipping:

Inventory:30,000
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Product details
Overview
LD6805K/20H,115 from NXP Semiconductors is a 2.0 V fixed-output, 150 mA low-dropout (LDO) regulator in a 1 × 1 mm DFN package, featuring 75 dB PSRR at 1 kHz, 250 mV dropout at full load, and high-ohmic (3-state) output during disable mode. It operates from 2.3 V to 5.5 V input and delivers ultra-low 40 µVRMS output noise for noise-sensitive analog and digital interfaces in portable electronics.
For engineers reviewing the LD6805K/20H,115 datasheet, LD6805K/20H,115 pinout, LD6805K/20H,115 application, or LD6805K/20H,115 equivalent, this LDO is selected for miniaturized power rails requiring stable 2.0 V supply with high ripple rejection, fast 150 µs turn-on time, and shutdown quiescent current of 0.1 µA - critical for battery-powered mobile devices and embedded peripherals.
Technical Context
The LD6805K/20H,115 implements a PMOS pass transistor architecture enabling ultra-low dropout and high PSRR without external compensation. Its internal voltage reference and error amplifier maintain ±0.5% output accuracy over temperature and load, while the enable input (active HIGH) controls a dedicated shutdown circuit that places the OUT pin in a high-impedance state - eliminating residual discharge paths.
This variant belongs to the LD6805K/xxH family, distinguished from /xxP versions by its high-ohmic disable behavior rather than auto-discharge. It requires a minimum 0.7 µF X7R ceramic output capacitor with ESR between 5 mΩ and 500 mΩ for stability, and supports operation across −40 °C to +85 °C ambient.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.0 V ±0.5% at 1 mA, ±3% over −40 °C to +85 °C - ensures precise biasing for 2.0 V logic and analog circuits. |
| Dropout Voltage | 250 mV at 150 mA - enables regulation from 2.25 V input, maximizing battery runtime in single-cell Li-ion or Li-poly systems. |
| PSRR | 75 dB at 1 kHz - suppresses switching noise from upstream DC-DC converters feeding sensitive RF or audio subsystems. |
| Output Noise | 40 µVRMS (10 Hz–100 kHz) - meets low-noise requirements for ADC references, PLL VCO supplies, and precision sensors. |
| Quiescent Current | 0.1 µA in shutdown (VEN ≤ 0.4 V) - minimizes leakage current in always-on standby modes for IoT endpoints. |
| Enable Threshold | VIH = 1.1 V min, VIL = 0.4 V max - compatible with 1.8 V and 3.3 V GPIO control without level-shifting. |
| Thermal Resistance | Rth(j-a) = 250 K/W - requires PCB copper thermal pad connection to GND for safe 150 mA operation at +85 °C ambient. |
Pinout & Package
LD6805K/20H,115 is housed in a DFN1010C-4 (SOT1194-1) plastic package measuring 1.0 × 1.0 × 0.55 mm, with an exposed thermal pad (TAB) on the underside electrically connected to GND. Thermal performance depends on soldering the TAB to a GND plane via multiple vias.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output voltage node | Delivers stable 2.0 V; high-impedance when EN = LOW - isolates downstream circuitry during sleep. |
| 2 - GND | Power and reference ground | Common return path for IN, OUT, and EN; must be connected to PCB GND plane for thermal and noise integrity. |
| 3 - EN | Active-HIGH enable input | Logic-controlled ON/OFF; drives internal shutdown circuit - no external pull-up required if driven by microcontroller GPIO. |
| 4 - IN | Unregulated input supply | Accepts 2.3–5.5 V; requires local 1 µF ceramic decoupling capacitor placed within 2 mm of the pin. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-high PSRR | 75 dB at 1 kHz - rejects noise from noisy switchers, enabling clean power for RF front-ends and high-resolution ADCs. |
| Low-noise output | 40 µVRMS (10 Hz–100 kHz) - eliminates need for post-regulation filtering in precision analog signal chains. |
| Fast start-up | 150 µs to 95% of 2.0 V - supports rapid wake-up sequences in low-power microcontroller applications. |
| High-ohmic disable | Open-circuit output state when disabled - prevents backfeeding and preserves voltage on shared rails during system sleep. |
| ESD robustness | 6 kV HBM - withstands handling and board-level ESD events without latch-up or parameter shift. |
Applications
| Smartphone Baseband Power | Digital Camera Sensor Bias |
|---|---|
Use Scenario: Supplies 2.0 V core voltage to baseband processor I/O banks in LTE smartphones operating from single-cell Li-ion battery. IC Role / Device Role / Timing Role: Primary LDO delivering regulated, low-noise 2.0 V rail with fast transient response to burst-mode data transmission. Use Value: High PSRR prevents GSM/UMTS switching noise from corrupting baseband signal integrity; 250 mV dropout extends usable battery range down to 2.25 V. |
Use Scenario: Powers CMOS image sensor analog front-end in compact digital still cameras where space and thermal budget are constrained. IC Role / Device Role / Timing Role: Low-noise 2.0 V bias source for pixel readout circuitry and column amplifiers during exposure and readout phases. Use Value: 40 µVRMS noise ensures <1 LSB noise floor in 12-bit image capture; 1 × 1 mm footprint enables placement adjacent to sensor die. |
| Portable Media Player Audio Codec | Bluetooth LE Peripheral Supply |
Use Scenario: Provides clean 2.0 V supply to stereo audio DAC and headphone amplifier in flash-based media players. IC Role / Device Role / Timing Role: Dedicated LDO for analog audio path, isolated from noisy digital supply domains via high-ohmic disable during pause mode. Use Value: 75 dB PSRR eliminates audible switching artifacts; 0.1 µA shutdown current preserves battery charge during multi-day idle periods. |
Use Scenario: Powers Bluetooth Low Energy SoC in wearable fitness trackers with aggressive duty-cycling and coin-cell battery constraints. IC Role / Device Role / Timing Role: Always-on 2.0 V rail for BLE radio and sensor hub, enabled only during active advertising/connection intervals. Use Value: Fast 150 µs startup synchronizes with BLE protocol timing; 250 K/W thermal resistance allows continuous 150 mA operation on 2-layer FR4. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B202MR-G | 2.0 V fixed, 150 mA, 200 mV dropout, 70 dB PSRR at 1 kHz, SOT-25 package (2.9 × 2.8 mm) | Larger footprint; lower PSRR reduces noise suppression in RF-sensitive designs | Select when board layout permits larger package and PSRR >72 dB is not required. |
| Richtek RT9013-20GB | 2.0 V fixed, 300 mA, 300 mV dropout, 65 dB PSRR at 1 kHz, DFN1010-4 (1.0 × 1.0 mm) package | Higher current but higher dropout and lower PSRR; no high-ohmic disable - outputs low during shutdown | Choose only if 300 mA load capability is needed and auto-discharge is acceptable for system isolation. |
Compared with XC6210B202MR-G and RT9013-20GB, LD6805K/20H,115 offers superior PSRR and true 3-state disable in the smallest footprint - making it optimal for space-constrained, noise-critical portable applications where output isolation during sleep is mandatory.
Availability
LD6805K/20H,115 is available at Aetrix Electronics and suitable for smartphone baseband power, digital camera sensor bias, portable media player audio codec, Bluetooth LE peripheral supply, and other portable electronics requiring stable component supply with tight thermal and noise constraints.
Supply support for LD6805K/20H,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets.
The LD6805 series was designed specifically for miniaturized portable electronics demanding ultra-small LDOs with high PSRR and low noise - targeting smart phones, wearables, and imaging modules where board area and power integrity are critical.
FAQ
What is the maximum input voltage rating for LD6805K/20H,115?
The absolute maximum input voltage for LD6805K/20H,115 is +6.0 V for 4 ms transients, per the datasheet limiting values table. For continuous operation, the recommended input range is 2.3 V to 5.5 V. Exceeding 5.5 V may cause permanent damage or degraded PSRR performance. Always verify input rail stability and transient margins in your design before finalizing the power architecture for LD6805K/20H,115.
Does LD6805K/20H,115 require an external output capacitor, and what are the specifications?
Yes, LD6805K/20H,115 requires an external ceramic output capacitor with minimum value 0.7 µF (recommended 1.0 µF), X7R dielectric, and ESR between 5 mΩ and 500 mΩ. This capacitor ensures loop stability and affects shutdown time. The capacitor must be placed within 2 mm of the OUT and GND pins. Using capacitors outside these specs risks oscillation or excessive overshoot during enable transitions - critical for reliable operation of LD6805K/20H,115 in production systems.
What is the thermal pad (TAB) connection requirement for LD6805K/20H,115?
The exposed thermal pad (TAB) on LD6805K/20H,115 is internally connected to GND and must be soldered to a PCB GND plane using ≥4 thermal vias (0.3 mm diameter) to an inner GND layer. Leaving the TAB unconnected degrades Rth(j-a) from 250 K/W to >350 K/W, risking thermal shutdown at 150 mA above 60 °C ambient. Proper TAB connection is mandatory to achieve rated current and reliability for LD6805K/20H,115 in real-world layouts.
How does the high-ohmic disable mode of LD6805K/20H,115 differ from auto-discharge variants?
When disabled (EN = LOW), LD6805K/20H,115 places the OUT pin in a high-impedance (3-state) condition, isolating downstream loads from the regulator. In contrast, /xxP variants use an internal pull-down transistor to actively discharge the output. This makes LD6805K/20H,115 ideal for systems where output voltage retention or bus isolation during sleep is required - a key differentiator confirmed in the LD6805 series datasheet for LD6805K/20H,115.
Is LD6805K/20H,115 RoHS compliant and halogen-free?
Yes, LD6805K/20H,115 is Pb-free, RoHS compliant, and free of halogen and antimony - meeting "dark green" compliance standards per the NXP product data sheet. This ensures environmental compliance for global consumer electronics shipments and aligns with IPC-1752 material declaration requirements. Full compliance documentation is available upon request for LD6805K/20H,115.
LD6805K/20H,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 4-UDFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 35 µA
- Current - Supply (Max):
- 150 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Transient Voltage
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1010C-4
LD6805K/20H,115 FAQ
1.How can I place an order for LD6805K/20H,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6805K/20H,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6805K/20H,115 reliable?
The price and inventory of LD6805K/20H,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6805K/20H,115 is usually 5 days.
3.What payment methods are accepted for LD6805K/20H,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6805K/20H,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LD6805K/20H,115?
LD6805K/20H,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6805K/20H,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6805K/20H,115?
For technical support, including LD6805K/20H,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6805K/20H,115 requirements.
6.How does Aetrix verify that LD6805K/20H,115 is sourced from the original manufacturer or authorized distributors?
All LD6805K/20H,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6805K/20H,115 meets industry standards.
7.What is the process for return or replacement of LD6805K/20H,115?
All LD6805K/20H,115 units undergo pre-shipment inspection (PSI). If there is an issue with LD6805K/20H,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6805K/20H,115 part is unused and in its original packaging.
Return procedure for LD6805K/20H,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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