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NXP Semiconductors LD6805K/20P,115
- Part No.:
- LD6805K/20P,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 4-UDFN Exposed Pad
- Datasheet:
-
LD6805K/20P,115.pdf
- Description:
- IC REG LIN 2V 150MA DFN1010C-4
- Quantity:
- Payment:
- Shipping:
Inventory:50,000
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Product details
Overview
LD6805K/20P,115 from NXP Semiconductors is a 2.0 V fixed-output, 150 mA low-dropout (LDO) regulator in a 1 × 1 mm DFN package, featuring 75 dB PSRR at 1 kHz, 250 mV dropout at full load, and auto-discharge functionality via integrated pull-down transistor. It operates from 2.3 V to 5.5 V input and delivers ultra-low 40 µVRMS output noise for noise-sensitive analog rails in portable electronics.
For engineers reviewing the LD6805K/20P,115 datasheet, LD6805K/20P,115 pinout, LD6805K/20P,115 application, or LD6805K/20P,115 equivalent, this LDO is selected for compact battery-powered systems requiring stable 2.0 V supply with fast enable control (150 µs startup), high PSRR filtering, and controlled discharge during shutdown.
Technical Context
The LD6805K/20P,115 integrates a precision voltage reference, error amplifier, and PMOS pass transistor in monolithic silicon. Its auto-discharge function uses an internal ~100 Ω pull-down switch on the OUT pin when EN is low, ensuring rapid output voltage decay without external components.
It employs a stable internal compensation network compatible with 1.0 µF ±30% X7R ceramic output capacitors and achieves 75 dB power supply rejection up to 1 kHz-critical for isolating sensitive analog circuitry (e.g., ADC references, RF bias rails) from noisy digital or switching power supplies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.0 V ±2% over −40 °C to +85 °C; enables direct replacement of 2.0 V logic or analog supply rails without external feedback. |
| Dropout Voltage | 250 mV at 150 mA load; allows operation with only 2.25 V input for 2.0 V output, maximizing battery runtime in single-cell Li-ion or Li-poly systems. |
| PSRR | 75 dB at 1 kHz; suppresses ripple from upstream DC-DC converters or noisy system rails, reducing need for additional LC filtering stages. |
| Output Noise | 40 µVRMS (10 Hz–100 kHz); ensures clean biasing for precision op-amps, PLLs, and high-resolution ADCs without added noise-reduction circuitry. |
| Quiescent Current | 0.1 µA typical in shutdown (EN ≤ 0.4 V); minimizes leakage current in always-on subsystems like real-time clocks or wake-up controllers. |
| Enable Threshold | VIH = 1.1 V min, VIL = 0.4 V max; compatible with 1.8 V and 3.3 V GPIOs without level-shifting, simplifying host microcontroller interface. |
| Thermal Resistance | Rth(j-a) = 250 K/W (typical); requires minimal PCB copper area for thermal management in space-constrained mobile designs. |
Pinout & Package
LD6805K/20P,115 is housed in a DFN1010C-4 (SOT1194-1) plastic package: 1.0 × 1.0 × 0.55 mm body with exposed thermal pad (TAB) on underside, rated for −40 °C to +85 °C ambient operation. The TAB is internally connected to GND and must be soldered to a PCB ground plane for optimal thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OUT | Regulated output voltage node | Delivers 2.0 V to load; includes integrated 100 Ω pull-down transistor active during disable (EN = LOW) for auto-discharge. |
| 2 - GND | Supply ground reference | Common return path for input, output, and internal circuitry; connects directly to exposed TAB for thermal conduction. |
| 3 - EN | Active-HIGH enable input | Controls regulator state: HIGH ≥1.1 V enables regulation; LOW ≤0.4 V disables output and activates pull-down. |
| 4 - IN | Unregulated input voltage source | Accepts 2.3–5.5 V; feeds internal pass transistor; requires local 1 µF ceramic decoupling capacitor per datasheet recommendation. |
Key Features
| Feature | Design Value |
|---|---|
| Auto-discharge function | Integrated 100 Ω pull-down on OUT pin during disable eliminates need for external discharge resistor, saving board space and BOM cost. |
| Ultra-low output noise | 40 µVRMS (10 Hz–100 kHz) enables direct powering of noise-critical analog blocks without post-regulation filtering. |
| High PSRR at 1 kHz | 75 dB rejection of switching converter ripple allows co-location with DC-DC sources in dense portable layouts. |
| Low shutdown current | 0.1 µA typical quiescent current in disabled state extends battery life in standby or sleep modes. |
| Small 1 × 1 mm footprint | DFN1010C-4 package reduces PCB area by >60% vs. SOT-23 alternatives, supporting miniaturization in smartphones and wearables. |
Applications
| Smartphone Baseband Power | Digital Camera Sensor Bias |
|---|---|
|
Use Scenario: Supplies 2.0 V to baseband processor I/O banks in LTE/5G handsets where input rail shares noise with RF power amplifiers and switching regulators. IC Role / Device Role / Timing Role: Low-noise, high-PSRR LDO providing clean 2.0 V supply; enabled/disabled synchronously with processor sleep/wake cycles. Use Value: Prevents digital switching noise from corrupting baseband signal integrity, improving receiver sensitivity and reducing bit error rate. |
Use Scenario: Powers CMOS image sensor analog front-end (AFE) and column ADC in compact digital still cameras. IC Role / Device Role / Timing Role: Stable 2.0 V bias source with fast 150 µs startup; auto-discharge clears residual charge before next frame capture. Use Value: Eliminates image lag and fixed-pattern noise caused by slow discharge of sensor parasitic capacitance. |
| Portable Media Player Audio Codec | GPS Receiver LNA Bias |
|
Use Scenario: Delivers 2.0 V to stereo audio codec's DAC and headphone driver in MP3 players and Bluetooth earbuds. IC Role / Device Role / Timing Role: Ultra-low-noise LDO placed adjacent to audio IC; enabled only during playback to minimize idle power. Use Value: Reduces audible hiss and improves SNR by suppressing broadband noise that would otherwise modulate audio signals. |
Use Scenario: Provides 2.0 V bias to low-noise amplifier (LNA) in personal navigation devices with integrated GPS/GNSS receivers. IC Role / Device Role / Timing Role: High-PSRR regulator rejecting noise from MCU and display drivers; auto-discharge prevents LNA latch-up during cold start. Use Value: Enhances weak-signal acquisition time and tracking stability by maintaining LNA linearity under dynamic system noise conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B202MR-G | 2.0 V fixed output, 150 mA, 200 mV dropout, but no auto-discharge; PSRR = 65 dB @ 1 kHz; 0.6 µF min output cap. | Lacks integrated pull-down; requires external resistor for discharge, increasing component count and leakage risk. | Select when board space permits external discharge circuit and PSRR >70 dB is not required. |
| Richtek RT9013-20GB | 2.0 V fixed output, 250 mA, 220 mV dropout, 70 dB PSRR @ 1 kHz, 45 µVRMS noise; no auto-discharge; SOT-23-5 package. | Larger 2.9 × 1.6 mm SOT-23-5 footprint; higher output current irrelevant for 150 mA use cases; no discharge control. | Choose only if higher current headroom is needed and 1 × 1 mm DFN is not mandatory. |
Compared with XC6210B202MR-G and RT9013-20GB, LD6805K/20P,115 uniquely combines 1 × 1 mm size, 75 dB PSRR, and integrated auto-discharge-enabling smaller, quieter, and more responsive power sequencing in space- and noise-constrained portable designs.
Availability
LD6805K/20P,115 is available at Aetrix Electronics and suitable for smartphone baseband power, digital camera sensor bias, portable media player audio codecs, and GPS receiver LNA bias requiring stable component supply across high-volume consumer electronics production.
Supply support for LD6805K/20P,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets.
The LD6805 series belongs to NXP's high-performance analog power management portfolio, designed specifically for ultra-compact, low-noise, and high-PSRR regulation in battery-powered portable electronics.
FAQ
What is the output voltage tolerance of LD6805K/20P,115 over temperature?
The LD6805K/20P,115 maintains a 2.0 V output with ±2% tolerance over the full operating temperature range of −40 °C to +85 °C, as specified in Table 8 of the datasheet. This accuracy is achieved using a trimmed internal voltage reference and process-compensated error amplifier, ensuring reliable operation in consumer-grade portable environments without external calibration.
Does LD6805K/20P,115 require an external discharge resistor?
No, LD6805K/20P,115 does not require an external discharge resistor. It integrates a ~100 Ω pull-down transistor on the OUT pin that activates automatically when the EN pin is driven LOW, enabling rapid discharge of output capacitance without additional components-a key differentiator from standard LDOs like the XC6210B202MR-G.
What is the minimum recommended output capacitor for LD6805K/20P,115?
The minimum recommended output capacitor for LD6805K/20P,115 is 0.7 µF with ±30% tolerance, though 1.0 µF X7R ceramic is the preferred value per Table 9. Using less than 0.7 µF risks instability and excessive overshoot during load transients, while exceeding the 5–500 mΩ ESR range may degrade transient response or PSRR performance.
Can LD6805K/20P,115 operate with a 2.3 V input to deliver 2.0 V output?
Yes, LD6805K/20P,115 can operate with a 2.3 V input to deliver 2.0 V output because its maximum dropout voltage is 250 mV at 150 mA. At 2.3 V input, the 300 mV headroom exceeds the worst-case dropout, ensuring regulation remains active across temperature and load variations-critical for single-cell Li-ion applications near end-of-discharge.
Is the thermal pad (TAB) of LD6805K/20P,115 electrically connected?
Yes, the thermal pad (TAB) of LD6805K/20P,115 is internally connected to GND, as confirmed in Section 2.2 Pin Description. It must be soldered to a PCB ground plane to achieve the specified Rth(j-a) of 250 K/W; leaving it unconnected degrades thermal performance and may cause premature thermal shutdown under sustained 150 mA load.
LD6805K/20P,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 4-UDFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 35 µA
- Current - Supply (Max):
- 150 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Transient Voltage
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1010C-4
LD6805K/20P,115 FAQ
1.How can I place an order for LD6805K/20P,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6805K/20P,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6805K/20P,115 reliable?
The price and inventory of LD6805K/20P,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6805K/20P,115 is usually 5 days.
3.What payment methods are accepted for LD6805K/20P,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6805K/20P,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LD6805K/20P,115?
LD6805K/20P,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6805K/20P,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6805K/20P,115?
For technical support, including LD6805K/20P,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6805K/20P,115 requirements.
6.How does Aetrix verify that LD6805K/20P,115 is sourced from the original manufacturer or authorized distributors?
All LD6805K/20P,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6805K/20P,115 meets industry standards.
7.What is the process for return or replacement of LD6805K/20P,115?
All LD6805K/20P,115 units undergo pre-shipment inspection (PSI). If there is an issue with LD6805K/20P,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6805K/20P,115 part is unused and in its original packaging.
Return procedure for LD6805K/20P,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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