My Inquiry
My Account
NXP Semiconductors LD6805K/21P,115
- Part No.:
- LD6805K/21P,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 4-UDFN Exposed Pad
- Datasheet:
-
LD6805K/21P,115.pdf
- Description:
- IC REG LIN 2.1V 150MA DFN1010C-4
- Quantity:
- Payment:
- Shipping:
Inventory:70,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LD6805K/21P,115 from NXP Semiconductors is a 2.1 V fixed-output, 150 mA low-dropout (LDO) regulator in a 1 × 1 mm DFN package, featuring 75 dB PSRR at 1 kHz, 250 mV dropout at full load, and auto-discharge functionality via integrated pull-down transistor. It operates from 2.3 V to 5.5 V input and delivers ultra-low 40 µVRMS output noise for noise-sensitive analog rails in portable electronics.
For engineers reviewing the LD6805K/21P,115 datasheet, LD6805K/21P,115 pinout, LD6805K/21P,115 application, or LD6805K/21P,115 equivalent, this page provides verified specifications, validated pin functions, confirmed thermal and noise performance, and real-world use cases in mobile power management - all grounded in NXP's official Rev. 2 product data sheet.
Technical Context
The LD6805K/21P,115 implements a CMOS-based LDO architecture with internal voltage reference, error amplifier, and pass transistor optimized for high PSRR and fast transient response. Its enable input (active HIGH) controls both regulation and the dedicated pull-down switch that actively discharges the output capacitor during shutdown.
This device integrates over-current protection, thermal shutdown, and 6 kV HBM ESD protection. The 1 × 1 × 0.55 mm DFN1010C-4 (SOT1194-1) package features an exposed thermal pad (TAB) connected internally to GND, enabling efficient heat dissipation in space-constrained PCB layouts.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.1 V ±2% over −40 °C to +85 °C; ensures stable core supply for 2.1 V logic or analog circuitry without external feedback. |
| Dropout Voltage | 250 mV at 150 mA; enables operation with only 2.35 V input for 2.1 V output, maximizing battery runtime in single-cell Li-ion systems. |
| PSRR | 75 dB at 1 kHz; suppresses switching noise from upstream DC-DC converters feeding sensitive RF or audio subsystems. |
| Output Noise | 40 µVRMS (10 Hz–100 kHz); meets low-noise requirements for ADC references, PLL VCO supplies, and precision sensor interfaces. |
| Quiescent Current | 0.1 µA typical in shutdown mode; minimizes leakage current in always-on standby circuits for extended battery life. |
| Enable Threshold | VIH = 1.1 V min, VIL = 0.4 V max; compatible with 1.8 V and 3.3 V GPIO control without level-shifting. |
| Startup Time | 150 µs to 95% of 2.1 V; supports fast wake-up sequences in power-gated mobile SoC domains. |
Pinout & Package
LD6805K/21P,115 is housed in a DFN1010C-4 (SOT1194-1) plastic package measuring 1.0 × 1.0 × 0.55 mm with an exposed thermal pad (TAB) on the underside, electrically tied to GND. Thermal performance requires soldering the TAB to a PCB ground plane for optimal junction-to-ambient thermal resistance (Rth(j-a) ≈ 250 K/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: OUT | Regulated output voltage node | Delivers 2.1 V to load; connects to 1 µF X7R ceramic capacitor for stability and controlled discharge via internal pull-down when disabled. |
| 2: GND | Supply ground reference | Common return path for input, output, and internal circuitry; must be connected to PCB ground plane and thermally coupled to TAB. |
| 3: EN | Active-HIGH enable input | Logic-controlled startup/shutdown; drives internal pass transistor and pull-down switch; no external pull-up required. |
| 4: IN | Unregulated input voltage supply | Accepts 2.3–5.5 V; requires local 1 µF ceramic decoupling close to pin to maintain PSRR and transient response. |
Key Features
| Feature | Design Value |
|---|---|
| Auto-discharge function | Integrated 100 Ω pull-down transistor on OUT pin ensures rapid, controlled discharge of output capacitance during disable - critical for safe power sequencing in multi-rail systems. |
| Ultra-high PSRR | 75 dB at 1 kHz and >40 dB up to 100 kHz enables clean power delivery to RF transceivers and high-resolution ADCs without additional filtering. |
| Low-noise regulation | 40 µVRMS noise (10 Hz–100 kHz) eliminates need for post-LDO LC filters in precision analog signal chains. |
| Miniaturized thermal package | DFN1010C-4 footprint (1 mm²) with exposed GND pad supports high-density layouts in smartphones and wearables while maintaining 150 mA capability. |
| Robust ESD protection | 6 kV HBM rating allows direct integration into handheld devices without external ESD diodes on power rails. |
Applications
| Smartphone Baseband Power | Digital Camera Image Sensor Bias |
|---|---|
Use Scenario: Supplying 2.1 V bias to baseband processor I/O banks during active communication modes. IC Role / Device Role / Timing Role: Primary LDO delivering regulated, low-noise 2.1 V rail with fast enable/disable for dynamic power gating. Use Value: Auto-discharge prevents back-powering of disabled domains; 75 dB PSRR isolates baseband from noisy PMIC switching noise. |
Use Scenario: Providing clean 2.1 V supply to CMOS image sensor analog front-end during exposure capture. IC Role / Device Role / Timing Role: Low-noise, low-dropout regulator ensuring stable reference for pixel readout and ADC conversion. Use Value: 40 µVRMS output noise directly improves image SNR; 150 µs startup enables precise timing-synchronized power activation. |
| Portable Media Player Audio Codec | Wearable Health Sensor Signal Chain |
Use Scenario: Powering DAC and headphone amplifier stages in battery-powered media players. IC Role / Device Role / Timing Role: Fixed-output LDO supplying low-distortion analog supply independent of battery voltage sag. Use Value: 250 mV dropout extends playback time near end-of-charge; 2.1 V matches common codec VDDA requirements. |
Use Scenario: Delivering stable 2.1 V to optical heart-rate sensor analog front-end in compact wearable form factors. IC Role / Device Role / Timing Role: Miniaturized, thermally efficient LDO supporting continuous low-power sensing with fast wake-up. Use Value: 1 mm² DFN package fits constrained PCB area; 0.1 µA shutdown current preserves coin-cell battery life for months. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6219B212MR-G | 2.1 V fixed output, 150 mA, 200 mV dropout, but lacks auto-discharge; PSRR = 65 dB @ 1 kHz. | No integrated pull-down; requires external discharge circuit for safe sequencing in multi-rail systems. | Select when auto-discharge is unnecessary and lower dropout is prioritized over noise rejection. |
| Richtek RT9013-21GB | 2.1 V fixed output, 150 mA, 300 mV dropout, 70 dB PSRR @ 1 kHz, 50 µVRMS noise, includes enable but no auto-discharge. | Higher dropout and noise than LD6805K/21P,115; suitable where board space allows larger 1.2 × 1.2 mm package. | Choose when cost sensitivity outweighs PSRR/noise requirements and thermal constraints permit larger footprint. |
Compared with XC6219B212MR-G and RT9013-21GB, LD6805K/21P,115 uniquely combines 75 dB PSRR, 40 µVRMS noise, and integrated auto-discharge in a 1 mm² package - making it optimal for space-constrained, noise-critical, and sequenced-power applications where output rail control is mandatory.
Availability
LD6805K/21P,115 is available at Aetrix Electronics and suitable for smartphone baseband power, digital camera sensor bias, portable media player audio codecs, and wearable health sensor signal chains requiring stable component supply, consistent parametric performance, and long-term lifecycle support.
Supply support for LD6805K/21P,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer electronics.
The LD6805 series belongs to NXP's high-PSRR, miniaturized LDO portfolio designed specifically for power integrity in portable and battery-powered devices where noise suppression, fast transient response, and ultra-small footprint are critical.
FAQ
What is the output voltage tolerance of LD6805K/21P,115 across temperature and load?
The LD6805K/21P,115 delivers a nominal 2.1 V output with ±2% tolerance over −40 °C to +85 °C ambient temperature and 1 mA to 150 mA load current. At +25 °C and 1 mA load, the variation is tighter at ±0.5%, ensuring precision for voltage-sensitive analog circuitry. This specification is guaranteed per NXP's official product data sheet Rev. 2.
Does LD6805K/21P,115 require an external output capacitor, and what type is recommended?
Yes, LD6805K/21P,115 requires a minimum 0.7 µF external ceramic output capacitor for stability, with 1.0 µF recommended. NXP specifies X7R dielectric with ±30% tolerance over −40 °C to +125 °C. The capacitor must have ESR between 5 mΩ and 500 mΩ; using a 1 µF X7R part ensures optimal PSRR, noise suppression, and controlled auto-discharge behavior in LD6805K/21P,115 designs.
How does the auto-discharge function work in LD6805K/21P,115 during shutdown?
When the EN pin is driven LOW, LD6805K/21P,115 disables regulation and activates an internal ~100 Ω pull-down transistor between OUT and GND. This actively discharges the output capacitor, preventing residual voltage from back-powering downstream circuitry. Shutdown time depends on output capacitance and is typically <300 µs for 1 µF - a key feature distinguishing LD6805K/21P,115 from standard high-impedance LDOs like the /xxH variant.
What is the thermal resistance (Rth(j-a)) of LD6805K/21P,115, and how can it be minimized?
The typical junction-to-ambient thermal resistance of LD6805K/21P,115 is 250 K/W under standard two-layer PCB conditions. To minimize Rth(j-a), the exposed thermal pad (TAB) must be soldered to a solid GND copper pour, and multiple vias should connect it to inner ground/power planes. Avoid solder mask over the pad, and use the recommended reflow profile per J-STD-020C for the 1.0 × 1.0 mm DFN1010C-4 package.
Is LD6805K/21P,115 RoHS compliant and halogen-free?
Yes, LD6805K/21P,115 is fully RoHS compliant and free of halogen and antimony, meeting NXP's "dark green" environmental standard. It contains no lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or polybrominated diphenyl ethers (PBDE). This compliance is documented in Section 1.2 of the official LD6805 series product data sheet.
LD6805K/21P,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 4-UDFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2.1V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 35 µA
- Current - Supply (Max):
- 150 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Transient Voltage
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1010C-4
LD6805K/21P,115 FAQ
1.How can I place an order for LD6805K/21P,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6805K/21P,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6805K/21P,115 reliable?
The price and inventory of LD6805K/21P,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6805K/21P,115 is usually 5 days.
3.What payment methods are accepted for LD6805K/21P,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6805K/21P,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LD6805K/21P,115?
LD6805K/21P,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6805K/21P,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6805K/21P,115?
For technical support, including LD6805K/21P,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6805K/21P,115 requirements.
6.How does Aetrix verify that LD6805K/21P,115 is sourced from the original manufacturer or authorized distributors?
All LD6805K/21P,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6805K/21P,115 meets industry standards.
7.What is the process for return or replacement of LD6805K/21P,115?
All LD6805K/21P,115 units undergo pre-shipment inspection (PSI). If there is an issue with LD6805K/21P,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6805K/21P,115 part is unused and in its original packaging.
Return procedure for LD6805K/21P,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LD6805K/21P,115 Tags
-
MIC5504-1.8YM5-TR
Microchip Technology
-
MIC5504-3.3YM5-TR
Microchip Technology
-
MIC5365-3.0YC5-TR
Microchip Technology
-
MIC5365-1.8YC5-TR
Microchip Technology
-
MIC5365-2.5YC5-TR
Microchip Technology
-
MIC5365-3.3YC5-TR
Microchip Technology
-
MIC5365-3.3YD5-TR
Microchip Technology
-
MIC5317-3.3YM5-TR
Microchip Technology
-
TLV1117LV33DCYR
Texas Instruments
-
MIC5317-3.3YMT-TZ
Microchip Technology
-
MIC5528-3.3YMT-TR
Microchip Technology
-
TLV75801PDRVR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
