NXP Semiconductors LD6805K/22P,115
- Part No.:
- LD6805K/22P,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 4-UDFN Exposed Pad
- Datasheet:
-
LD6805K/22P,115.pdf
- Description:
- IC REG LIN 2.2V 150MA DFN1010C-4
- Quantity:
- Payment:

- Shipping:

Inventory:50,000
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Product details
Overview
LD6805K/22P,115 from NXP Semiconductors is a 2.2 V fixed-output, 150 mA ultra-low-noise LDO regulator with 75 dB PSRR at 1 kHz, 250 mV dropout at full load, and auto-discharge functionality enabled via integrated pull-down transistor. It operates from 2.3 V to 5.5 V input and targets power-sensitive analog/digital interfaces in portable consumer devices.
For engineers reviewing the LD6805K/22P,115 datasheet, LD6805K/22P,115 pinout, LD6805K/22P,115 application, or LD6805K/22P,115 equivalent, this page delivers verified electrical parameters, thermal behavior, disable-mode output state, package dimensions, and real-world use cases - all confirmed for the exact variant LD6805K/22P (2.2 V, pull-down output) in SOT1194-1 package.
Technical Context
The LD6805K/22P,115 implements a PMOS pass transistor architecture enabling low dropout and high PSRR. Its enable circuitry drives the EN pin active-high (VIH ≥ 1.1 V), and its internal shutdown path activates a 100 Ω pull-down transistor on OUT during disable, ensuring rapid discharge of external capacitance.
Thermal performance relies on PCB copper area under the exposed thermal pad (TAB), which is internally connected to GND. The device's 40 µV RMS output noise (10 Hz–100 kHz) and ±0.5% output voltage accuracy over temperature support precision analog supply rails in mobile SoC subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.2 V ±0.5% at +25 °C; ±2% over −40 °C to +85 °C ambient |
| Max Output Current | 150 mA continuous; peak current up to 200 mA before foldback activation |
| Dropout Voltage | 250 mV at 150 mA load - enables operation with minimal VIN–VOUT margin |
| PSRR | 75 dB at 1 kHz - suppresses switching noise from upstream DC/DC converters |
| Output Noise | 40 µV RMS (10 Hz–100 kHz) - suitable for RF biasing and ADC reference supplies |
| Quiescent Current | 150 µA typical under load; 0.1 µA in shutdown - extends battery life in standby mode |
| Enable Threshold | VIH = 1.1 V min; VIL = 0.4 V max - compatible with 1.8 V and 3.3 V logic interfaces |
Pinout & Package
LD6805K/22P,115 is housed in a DFN1010C-4 (SOT1194-1) plastic package measuring 1.0 × 1.0 × 0.55 mm with an exposed thermal pad (TAB) on the underside, internally connected to GND. Recommended PCB layout connects the TAB to a solid GND plane for optimal thermal resistance (Rth(j-a) ≈ 250 K/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: OUT | Regulated output voltage node | Delivers stable 2.2 V; pulled low via 100 Ω internal transistor when EN = LOW |
| 2: GND | Power and reference ground | Common return for IN, OUT, EN; electrically tied to exposed TAB |
| 3: EN | Active-high enable control | Logic-compatible input; asserts regulation when ≥1.1 V; disables output otherwise |
| 4: IN | Unregulated input supply | Accepts 2.3–5.5 V; requires ≥0.7 µF ceramic capacitor with ESR 5–500 mΩ |
Key Features
| Feature | Design Value |
|---|---|
| Auto-discharge function | Integrated 100 Ω pull-down on OUT during disable - clears residual charge from downstream caps in <300 µs |
| Ultra-low output noise | 40 µV RMS (10 Hz–100 kHz) - minimizes jitter in clock buffers and SNR degradation in audio codecs |
| High PSRR at 1 kHz | 75 dB - rejects ripple from switching regulators without additional LC filtering |
| Low quiescent current in shutdown | 0.1 µA typical - reduces leakage in always-on subsystems like RTC or sensor hubs |
| ESD robustness | 6 kV HBM - eliminates need for external protection diodes in handheld assembly lines |
Applications
| Smartphone Baseband Power | Digital Camera Sensor Bias |
|---|---|
Use Scenario: Supplies clean 2.2 V bias to baseband processor I/O banks during LTE/5G transmission bursts. IC Role / Device Role / Timing Role: Low-noise post-regulator stabilizing switched-mode rail; maintains signal integrity during RF switching transients. Use Value: 75 dB PSRR prevents AM modulation of RF carriers by DC/DC switching noise; 40 µV noise avoids baseband ADC quantization errors. |
Use Scenario: Powers CMOS image sensor analog front-end requiring stable voltage during exposure readout. IC Role / Device Role / Timing Role: Precision LDO delivering regulated 2.2 V with fast startup (<150 µs) to synchronize with frame timing signals. Use Value: 250 mV dropout allows use of 2.45 V intermediate rail; auto-discharge ensures pixel reset completes before next frame begins. |
| Portable Media Player Audio DAC | Bluetooth LE SoC Core Supply |
Use Scenario: Provides ultra-low-noise 2.2 V supply to stereo DAC in battery-powered media players. IC Role / Device Role / Timing Role: Analog supply rail isolator; decouples DAC from noisy digital domain supplies. Use Value: 40 µV RMS noise directly translates to >105 dB SNR; 0.1 µA shutdown current preserves battery during pause mode. |
Use Scenario: Powers 2.2 V core rail of Bluetooth 5.0 SoC during advertising interval wakeups. IC Role / Device Role / Timing Role: Fast-enabling LDO supporting duty-cycled operation; auto-discharge prevents leakage through BLE radio bias networks. Use Value: 150 µs startup time meets BLE sub-millisecond wakeup requirements; 100 Ω pull-down discharges 1 µF decoupling cap in <300 µs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B222MR-G | 2.2 V fixed, 150 mA, 70 dB PSRR @ 1 kHz, no auto-discharge; SOT-25 package (2.9 × 2.8 mm) | Lacks pull-down transistor - requires external discharge path for same timing behavior | Select if board space permits larger package and system design includes discrete discharge circuitry |
| Richtek RT9013-22GB | 2.2 V fixed, 300 mA, 65 dB PSRR @ 1 kHz, 250 mV dropout, no auto-discharge; SOT-23-5 package | Higher current rating but lower PSRR and no integrated discharge - increases BOM count | Choose when higher load headroom is needed and PSRR >70 dB is not required for RF coexistence |
Compared with XC6210B222MR-G and RT9013-22GB, LD6805K/22P,115 uniquely combines 75 dB PSRR, 2.2 V precision, and monolithic auto-discharge in a 1.0 mm² footprint - eliminating external components while meeting stringent noise and timing requirements in ultra-compact portable designs.
Availability
LD6805K/22P,115 is available at Aetrix Electronics and suitable for smartphone baseband power, digital camera sensor bias, portable media player audio DAC, and Bluetooth LE SoC core supply requiring stable component supply, consistent parametric performance, and long-term lifecycle support.
Supply support for LD6805K/22P,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets.
The LD6805 series belongs to NXP's ultra-miniature LDO portfolio, designed specifically for space-constrained portable electronics where high PSRR, low noise, and fast enable/disable transitions are critical for RF and analog subsystem integrity.
FAQ
What is the exact output voltage tolerance of LD6805K/22P,115 across temperature?
The LD6805K/22P,115 delivers 2.2 V with ±0.5% tolerance at +25 °C and ±2% over the full operating range of −40 °C to +85 °C ambient temperature. This specification is guaranteed per Table 8 in the official NXP product data sheet Rev. 2 (2012), and applies specifically to the LD6805K/22P variant with pull-down output functionality.
Does LD6805K/22P,115 require an external capacitor on the EN pin?
No, LD6805K/22P,115 does not require an external capacitor on the EN pin. The enable input is CMOS-compatible with VIH ≥ 1.1 V and VIL ≤ 0.4 V, and exhibits negligible input current (<100 nA). External filtering is unnecessary unless system-level EMI immunity mandates it - the device's internal enable circuitry is fully self-contained and validated for direct MCU GPIO connection.
What is the thermal resistance (Rth(j-a)) of LD6805K/22P,115 under standard PCB conditions?
The typical junction-to-ambient thermal resistance Rth(j-a) of LD6805K/22P,115 is 250 K/W when mounted on a two-layer PCB with recommended copper layout per Figure 9 in the datasheet. This value assumes the exposed TAB is soldered to a solid GND plane; performance degrades significantly if the TAB is left unconnected or routed with insufficient copper area.
Can LD6805K/22P,115 be used with ceramic output capacitors smaller than 1 µF?
Yes - LD6805K/22P,115 supports output capacitance as low as 0.7 µF (±30% tolerance), per Table 9. However, using 1.0 µF X7R ceramic is recommended to ensure stability across −40 °C to +125 °C and minimize shutdown time. Capacitances below 0.7 µF risk instability and are not characterized or guaranteed.
How does the auto-discharge function of LD6805K/22P,115 behave during disable?
When EN is driven LOW, LD6805K/22P,115 activates an internal 100 Ω pull-down transistor between OUT and GND, discharging external capacitive loads in under 300 µs (typical). This behavior is exclusive to the 'P' suffix variants (e.g., LD6805K/22P) and is confirmed in Figures 2 and 4, and Table 8 parameter Rpd, distinguishing it from 'H'-suffix high-impedance disable variants.
LD6805K/22P,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 4-UDFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2.2V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 35 µA
- Current - Supply (Max):
- 150 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Transient Voltage
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1010C-4
LD6805K/22P,115 FAQ
1.How can I place an order for LD6805K/22P,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6805K/22P,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6805K/22P,115 reliable?
The price and inventory of LD6805K/22P,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6805K/22P,115 is usually 5 days.
3.What payment methods are accepted for LD6805K/22P,115?
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4.How is shipping managed for LD6805K/22P,115?
LD6805K/22P,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6805K/22P,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6805K/22P,115?
For technical support, including LD6805K/22P,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6805K/22P,115 requirements.
6.How does Aetrix verify that LD6805K/22P,115 is sourced from the original manufacturer or authorized distributors?
All LD6805K/22P,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6805K/22P,115 meets industry standards.
7.What is the process for return or replacement of LD6805K/22P,115?
All LD6805K/22P,115 units undergo pre-shipment inspection (PSI). If there is an issue with LD6805K/22P,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6805K/22P,115 part is unused and in its original packaging.
Return procedure for LD6805K/22P,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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