NXP Semiconductors LD6805K/28P,115
- Part No.:
- LD6805K/28P,115
- Manufacturer:
- NXP Semiconductors
- Package:
- 4-UDFN Exposed Pad
- Datasheet:
-
LD6805K/28P,115.pdf
- Description:
- IC REG LIN 2.8V 150MA DFN1010C-4
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LD6805K/28P,115 from NXP Semiconductors is a 2.8 V fixed-output, 150 mA low-dropout (LDO) regulator in a 1 × 1 mm DFN package, featuring 75 dB PSRR at 1 kHz, 250 mV dropout at full load, and auto-discharge functionality via integrated pull-down transistor. It delivers ultra-low noise (40 µV RMS, 10 Hz–100 kHz) for powering sensitive analog and digital circuitry in space-constrained portable devices.
For engineers reviewing the LD6805K/28P,115 datasheet, LD6805K/28P,115 pinout, LD6805K/28P,115 application, or LD6805K/28P,115 equivalent, this page provides verified electrical parameters, thermal behavior, enable timing (150 µs startup), shutdown characteristics (300 µs discharge), and real-world design implications of its auto-discharge function and high-PSRR regulation.
Technical Context
The LD6805K/28P,115 integrates a precision voltage reference, error amplifier, and PMOS pass transistor with active current limiting and thermal shutdown. Its enable input (active HIGH, VIH ≥ 1.1 V) controls both regulation and the internal 100 Ω pull-down switch that actively discharges the output capacitor during disable-critical for fast power sequencing in multi-rail systems.
This variant belongs to the LD6805K/xxP subfamily, distinguishing it from /xxH versions by its low-ohmic disabled-state output. Its PSRR profile maintains ≥70 dB suppression up to 10 kHz, and its stability is guaranteed with 1 µF X7R ceramic output capacitance (ESR 5–500 mΩ), enabling robust performance under dynamic load transients.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.8 V ±2% over −40 °C to +85 °C; ensures stable biasing for 2.8 V logic, RF front-ends, or sensor interfaces without external feedback. |
| Dropout Voltage | 250 mV at 150 mA; enables operation from 3.05 V input, minimizing wasted headroom in battery-powered systems. |
| PSRR | 75 dB at 1 kHz; suppresses switching noise from upstream DC-DC converters, protecting noise-sensitive ADCs or PLLs. |
| Output Noise | 40 µV RMS (10 Hz–100 kHz); supports high-resolution analog signal chains where LDO noise directly impacts SNR. |
| Quiescent Current | 0.1 µA typical in shutdown (VEN ≤ 0.4 V); extends battery life in always-on standby modes. |
| Startup Time | 150 µs to 95% of 2.8 V (CL = 1 µF); meets fast wake-up requirements in mobile SoC power domains. |
| Shutdown Discharge | 300 µs to 5% of 2.8 V (CL = 1 µF) via 100 Ω internal pull-down; eliminates hold-up voltage that could delay system reset or cause latch-up. |
Pinout & Package
LD6805K/28P,115 uses the DFN1010C-4 (SOT1194-1) package: 1 × 1 × 0.55 mm body with exposed thermal pad (TAB) on underside, rated for 250 K/W junction-to-ambient thermal resistance on a two-layer PCB. The TAB must be connected to GND for optimal thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: OUT | Regulated output voltage node | Delivers 2.8 V to load; connects to 1 µF X7R ceramic capacitor; pulled low via 100 Ω transistor when EN = LOW. |
| 2: GND | Supply ground reference | Common return for IN, OUT, and EN; must be tied to PCB ground plane and thermally coupled to TAB. |
| 3: EN | Enable control input (active HIGH) | Drives regulation and auto-discharge; accepts 1.1–5.5 V logic; <0.4 V disables device and activates pull-down. |
| 4: IN | Unregulated input supply | Accepts 2.3–5.5 V; requires local 1 µF ceramic bypass; dropout limited to 250 mV at 150 mA load. |
Key Features
| Feature | Design Value |
|---|---|
| Auto-discharge function | Integrated 100 Ω pull-down transistor actively discharges output capacitor during disable, eliminating residual voltage that could interfere with power sequencing or cause back-powering. |
| Ultra-high PSRR | 75 dB at 1 kHz and >70 dB up to 10 kHz enables clean power delivery to RF ICs, audio codecs, and precision ADCs even when sharing noisy DC-DC rails. |
| Low-noise regulation | 40 µV RMS output noise (10 Hz–100 kHz) minimizes jitter in clock buffers and preserves dynamic range in analog front-ends. |
| Miniaturized thermal package | DFN1010C-4 (1 × 1 mm) with exposed GND tab achieves 250 K/W θJA, supporting 150 mA continuous output in ultra-thin mobile PCBs without heatsinks. |
| Robust ESD protection | 6 kV HBM ESD rating on all pins allows safe handling and assembly in standard manufacturing environments without additional protection circuitry. |
Applications
| Smartphone Baseband Power | Digital Camera Sensor Bias |
|---|---|
|
Use Scenario: Supplying 2.8 V to baseband processor I/O banks and RF transceiver analog sections in LTE/5G handsets. IC Role / Device Role / Timing Role: Primary LDO delivering low-noise, sequenced power with fast startup and controlled discharge during sleep mode transitions. Use Value: Prevents cross-talk between RF and digital domains via 75 dB PSRR and eliminates reset glitches via 300 µs auto-discharge. |
Use Scenario: Providing stable 2.8 V bias to CMOS image sensor analog pixel arrays and column ADCs in compact digital still cameras. IC Role / Device Role / Timing Role: Low-noise, low-drift voltage source ensuring consistent sensor gain and minimal fixed-pattern noise. Use Value: 40 µV RMS noise and ±2% output accuracy maintain image SNR and color fidelity across temperature and load variation. |
| Portable Media Player Audio DAC | Wearable Health Monitor Analog Front-End |
|
Use Scenario: Powering stereo audio DACs and headphone amplifiers in battery-operated media players requiring clean, quiet supply rails. IC Role / Device Role / Timing Role: Dedicated LDO isolating DAC core from noisy system rails, with fast turn-on to support instant playback. Use Value: 150 µs startup time enables immediate audio output after wake-up; 75 dB PSRR prevents audible switching artifacts. |
Use Scenario: Regulating 2.8 V for ECG/PPG analog front-end circuits in ultra-small wearable patches with strict size and power constraints. IC Role / Device Role / Timing Role: Miniature, low-quiescent LDO supplying precision analog blocks while enabling rapid power cycling to extend battery life. Use Value: 0.1 µA shutdown current and 1 × 1 mm footprint maximize runtime and board area efficiency in coin-cell-powered designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6219B282MR-G | 2.8 V fixed output, 150 mA, 70 dB PSRR at 1 kHz, no auto-discharge; SOT-25 package (2.9 × 1.6 mm). | Lacks pull-down transistor; requires external discharge circuit for fast shutdown sequencing. | Select when board space permits larger package and auto-discharge is not required for system-level power management. |
| Richtek RT9013-28GB | 2.8 V fixed output, 500 mA, 65 dB PSRR at 1 kHz, 25 µA quiescent current in operation; SOT-23-5 package. | Higher current capability but lower PSRR and no integrated discharge path; larger footprint than DFN1010C-4. | Choose when higher load current is needed and PSRR >70 dB is not critical for the target analog circuitry. |
Compared with XC6219B282MR-G and RT9013-28GB, LD6805K/28P,115 uniquely combines ultra-miniature 1 × 1 mm packaging, industry-leading 75 dB PSRR, and integrated auto-discharge-making it optimal for space-constrained, noise-sensitive, and fast-sequencing portable applications where those three attributes are simultaneously required.
Availability
LD6805K/28P,115 is available at Aetrix Electronics and suitable for smartphone baseband power, digital camera sensor bias, portable media player audio DACs, wearable health monitor analog front-ends, and other portable electronics requiring stable component supply with tight thermal and noise constraints.
Supply support for LD6805K/28P,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets.
The LD6805 series was designed specifically for ultra-compact, high-PSRR power management in battery-powered portable electronics-emphasizing miniaturization, noise immunity, and intelligent power sequencing via features like auto-discharge.
FAQ
What is the output voltage tolerance of LD6805K/28P,115 over temperature?
The LD6805K/28P,115 guarantees ±2% output voltage accuracy over the full operating temperature range of −40 °C to +85 °C. At +25 °C, the tolerance tightens to ±0.5%, and the device exhibits excellent line and load regulation (≤0.01%/mA load regulation error), ensuring stable 2.8 V delivery across varying input and load conditions. This accuracy is critical for powering voltage-sensitive analog circuits in portable devices.
Does LD6805K/28P,115 require an external discharge resistor for shutdown?
No, LD6805K/28P,115 does not require an external discharge resistor. It integrates a 100 Ω pull-down transistor on the OUT pin that activates automatically when the EN pin is driven LOW, discharging the output capacitor in 300 µs (with 1 µF load). This auto-discharge function eliminates hold-up voltage and simplifies power sequencing in multi-rail systems without adding external components.
What is the minimum recommended output capacitor for stable operation of LD6805K/28P,115?
The LD6805K/28P,115 requires a minimum 0.7 µF X7R ceramic capacitor on the OUT pin for stable operation, with 1.0 µF recommended. The capacitor must have an ESR between 5 mΩ and 500 mΩ. Using a 1 µF X7R part ensures optimal transient response, PSRR performance, and startup/shutdown timing-verified across −40 °C to +85 °C per the official NXP datasheet.
How does the PSRR of LD6805K/28P,115 compare to standard LDOs?
LD6805K/28P,115 delivers 75 dB PSRR at 1 kHz-significantly higher than typical LDOs (often 50–65 dB at 1 kHz). Its PSRR remains above 70 dB up to 10 kHz, making it exceptionally effective at suppressing ripple from switching DC-DC converters. This performance is achieved through optimized internal compensation and a high-gain error amplifier, directly benefiting noise-sensitive applications like RF transceivers and precision ADCs.
Is LD6805K/28P,115 compatible with lead-free reflow soldering processes?
Yes, LD6805K/28P,115 is qualified for lead-free reflow soldering per J-STD-020C. Its DFN1010C-4 package has a volume <350 mm³ and thickness <1.6 mm, requiring a peak reflow temperature of 260 °C. The device is RoHS compliant, halogen-free, and rated for MSL1 (unlimited floor life), supporting standard Pb-free manufacturing without special handling or baking requirements.
LD6805K/28P,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 4-UDFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2.8V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 150mA
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 35 µA
- Current - Supply (Max):
- 150 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Transient Voltage
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- DFN1010C-4
LD6805K/28P,115 FAQ
1.How can I place an order for LD6805K/28P,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6805K/28P,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6805K/28P,115 reliable?
The price and inventory of LD6805K/28P,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6805K/28P,115 is usually 5 days.
3.What payment methods are accepted for LD6805K/28P,115?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6805K/28P,115 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LD6805K/28P,115?
LD6805K/28P,115 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6805K/28P,115 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6805K/28P,115?
For technical support, including LD6805K/28P,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6805K/28P,115 requirements.
6.How does Aetrix verify that LD6805K/28P,115 is sourced from the original manufacturer or authorized distributors?
All LD6805K/28P,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6805K/28P,115 meets industry standards.
7.What is the process for return or replacement of LD6805K/28P,115?
All LD6805K/28P,115 units undergo pre-shipment inspection (PSI). If there is an issue with LD6805K/28P,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6805K/28P,115 part is unused and in its original packaging.
Return procedure for LD6805K/28P,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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