NXP Semiconductors LD6805K/36P,115

Overview

LD6805K/36P,115 from NXP Semiconductors is a 3.6 V fixed-output, 150 mA low-dropout (LDO) regulator in a 1 × 1 mm DFN package, featuring 75 dB PSRR at 1 kHz, 250 mV dropout at full load, and auto-discharge functionality via integrated pull-down transistor. It delivers ultra-low noise (40 µV RMS, 10 Hz–100 kHz) and fast turn-on (150 µs), targeting power-sensitive analog/digital subsystems in portable consumer electronics.

For engineers reviewing the LD6805K/36P,115 datasheet, LD6805K/36P,115 pinout, LD6805K/36P,115 application, or LD6805K/36P,115 equivalent, this page provides verified electrical parameters, thermal behavior, disable-mode output state, PCB layout guidance for DFN1010C-4, and validated alternative LDOs with matching 3.6 V output and auto-discharge capability.

Technical Context

The LD6805K/36P,115 integrates a precision voltage reference, error amplifier, and PMOS pass transistor in monolithic silicon, enabling stable regulation across −40 °C to +85 °C ambient. Its enable input (active HIGH, VIH ≥ 1.1 V) controls both regulation and the internal 100 Ω pull-down switch that actively discharges the output during shutdown.

This architecture ensures rapid startup (150 µs to 95% of 3.6 V), tight line/load regulation (±0.1 %/V, 0.0025 %/mA), and high immunity to input ripple-critical for powering RF front-ends, ADC reference supplies, and camera sensor rails where supply noise directly impacts signal integrity.

Key Specifications

Pinout & Package

LD6805K/36P,115 uses the DFN1010C-4 (SOT1194-1) thermally enhanced plastic package: 1 × 1 × 0.55 mm body with exposed thermal pad (TAB) on underside, rated for 250 K/W junction-to-ambient thermal resistance under standard 2-layer PCB conditions.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with XC6219B362MR-G and RT9013-36GB, LD6805K/36P,115 delivers the highest PSRR (75 dB) and lowest shutdown current (0.1 µA) in its class, while its 100 Ω auto-discharge resistance enables faster output decay than RT9013-36GB-making it optimal for systems requiring rapid, deterministic power sequencing.

Availability

LD6805K/36P,115 is available at Aetrix Electronics and suitable for smartphone camera modules, portable medical sensors, wireless headset audio codecs, and GPS navigation modules requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for LD6805K/36P,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets with over 40 years of analog power management expertise.

The LD6805 series belongs to NXP's ultra-miniature, high-PSRR LDO portfolio designed specifically for space-constrained portable electronics where low noise, fast transient response, and active output discharge are mandatory for reliable system-level power sequencing.

FAQ

What is the maximum input voltage rating for LD6805K/36P,115?

The absolute maximum input voltage for LD6805K/36P,115 is +6.0 V for 4 ms transients, with recommended continuous operation between 2.3 V and 5.5 V. Exceeding 6.0 V-even briefly-may cause permanent damage per IEC 60134 limiting values. For sustained reliability in battery-powered designs, keep VIN ≤ 5.5 V, especially when using Li-ion cells with peak charge voltages up to 4.35 V.

Does LD6805K/36P,115 require an external output capacitor, and what are the specifications?

Yes, LD6805K/36P,115 requires an external output capacitor of 1.0 µF typical (minimum 0.7 µF, ±30% tolerance) with ESR between 5 mΩ and 500 mΩ. X7R dielectric ceramic capacitors are recommended to maintain stability across −40 °C to +125 °C. The capacitor value directly affects shutdown time: larger capacitance increases tsd(reg), so 1.0 µF balances stability and rapid discharge.

How does the auto-discharge function operate in LD6805K/36P,115 during shutdown?

When the EN pin is driven LOW (<0.4 V), LD6805K/36P,115 disables regulation and activates an internal 100 Ω pull-down transistor between OUT and GND. This provides a low-ohmic path that discharges the output capacitor in under 300 µs (measured with 1 µF CL), preventing residual voltage from interfering with downstream logic states or causing latch-up during system resets.

What is the thermal resistance (Rth(j-a)) of LD6805K/36P,115, and how can it be optimized?

The typical junction-to-ambient thermal resistance of LD6805K/36P,115 is 250 K/W on a standard two-layer PCB. To optimize thermal performance, solder the exposed TAB directly to a solid GND copper pour using ≥4 thermal vias (0.3 mm diameter) connecting to inner ground/power planes. Avoid solder mask over the TAB area, and ensure ≥100 mm² copper area beneath the package for effective heat spreading.

Is LD6805K/36P,115 compatible with lead-free reflow soldering processes?

Yes, LD6805K/36P,115 is qualified for lead-free reflow per J-STD-020C. Its DFN1010C-4 package (volume <350 mm³, thickness <1.6 mm) has a maximum peak reflow temperature of 260 °C. Use a stencil thickness of 75 µm for solder paste deposition, and follow the recommended footprint in Figure 9 to prevent solder bridging and ensure reliable thermal pad attachment.