NXP Semiconductors LD6806F/13P,115

Overview

LD6806F/13P,115 from NXP Semiconductors is a 1.3 V, 200 mA ultra-low-dropout linear regulator in SOT886 (XSON6) package with 80 mV dropout at full load, 30 µV_RMS output noise (10 Hz–100 kHz), and active-HIGH enable control. It delivers stable low-noise power for voltage-sensitive analog circuits in space-constrained mobile applications.

For engineers reviewing the LD6806F/13P,115 datasheet, LD6806F/13P,115 pinout, LD6806F/13P,115 application, or LD6806F/13P,115 equivalent, key selection criteria include its low-ohmic pull-down output stage during disable, thermal shutdown at 160 °C, ±0.5 % output voltage accuracy at +25 °C, and compatibility with 1 µF X7R ceramic output capacitors.

Technical Context

The LD6806F/13P,115 uses a PMOS pass transistor architecture enabling ultra-low dropout and high PSRR (−55 dB @ 1 kHz). Its internal reference generator and feedback loop maintain regulation across −40 °C to +85 °C ambient, with integrated thermal protection and current limiting.

Unlike the H-suffix variants, the P-suffix confirms inclusion of an on-chip pull-down transistor (R_pd = 100 Ω typical) that actively discharges the output node during disable, eliminating external discharge circuitry in battery-powered systems requiring fast, controlled rail collapse.

Key Specifications

Pinout & Package

LD6806F/13P,115 is housed in a leadless plastic XSON6 package (SOT886), measuring 1.0 mm × 1.45 mm × 0.5 mm, with exposed thermal pad for enhanced heat dissipation. Thermal resistance R_th(j-a) is 220 K/W on a standard two-layer PCB.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with XC6219B132MR-G and RT9013-13GB, LD6806F/13P,115 offers superior dropout (80 mV), lower noise (30 µV_RMS), and integrated pull-down - critical for miniaturized, battery-sensitive designs where rail collapse timing and PCB area are constrained.

Availability

LD6806F/13P,115 is available at Aetrix Electronics and suitable for mobile handset power management, wearable sensor hubs, and Bluetooth audio subsystems requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for LD6806F/13P,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets.

The LD6806 series belongs to NXP's ultra-low-noise, miniaturized LDO portfolio, designed specifically for space- and power-constrained portable electronics requiring high PSRR, fast transient response, and integrated safety features.

FAQ

What is the maximum input voltage rating for LD6806F/13P,115?

The absolute maximum input voltage for LD6806F/13P,115 is +6.0 V for 4 ms transients, with recommended continuous operation between 2.3 V and 5.5 V. Exceeding 6.0 V risks permanent damage to the internal PMOS pass device and reference circuitry. Operation above 5.5 V voids guaranteed specifications and may trigger overvoltage protection only if present - which is not specified for this device.

Does LD6806F/13P,115 require an external output capacitor, and what type is recommended?

Yes, LD6806F/13P,115 requires a minimum 1.0 µF X7R ceramic capacitor at the OUT pin for stability, with ESR between 5 mΩ and 500 mΩ. The datasheet specifies X7R dielectric for full −40 °C to +125 °C operation; NP0/C0G is acceptable but less common due to size constraints. Tantalum or aluminum electrolytic capacitors are not recommended due to ESR and reliability limitations.

How does the pull-down transistor in LD6806F/13P,115 behave during disable?

When EN is driven LOW (<0.4 V), LD6806F/13P,115 activates an internal 100 Ω (typical) NMOS pull-down transistor between OUT and GND, discharging the output capacitance to 10 % of nominal voltage within 300 µs. This eliminates hold-up time and prevents unintended back-powering of upstream circuitry - a key advantage over H-suffix variants that enter high-impedance state.

What is the thermal resistance (R_th(j-a)) of LD6806F/13P,115, and how does PCB layout affect it?

LD6806F/13P,115 has a typical R_th(j-a) of 220 K/W on a standard two-layer PCB. Layout significantly impacts this value: connecting all pins - especially the exposed thermal pad - to large copper areas, using multiple vias to inner ground/power planes, and avoiding solder mask under the package can reduce R_th(j-a) by up to 40 %. Poor thermal design may cause premature thermal shutdown at <150 mA load.

Is LD6806F/13P,115 compatible with lead-free reflow soldering processes?

Yes, LD6806F/13P,115 is fully compatible with lead-free reflow profiles per J-STD-020C. Its SOT886 package falls into the "<350 mm³ volume, <1.6 mm thickness" category, requiring a peak temperature of 260 °C. Moisture sensitivity level (MSL) is not explicitly stated in the provided datasheet, but NXP WLCSP and XSON packages are typically MSL3 - bake before reflow if exposed >168 hours at ambient conditions.