My Inquiry
My Account
NXP Semiconductors LD6806TD/23H,125
- Part No.:
- LD6806TD/23H,125
- Manufacturer:
- NXP Semiconductors
- Package:
- SC-74A, SOT-753
- Datasheet:
-
LD6806TD/23H,125.pdf
- Description:
- IC REG LINEAR 2.3V 200MA 5TSOP
- Quantity:
- Payment:
- Shipping:
Inventory:36,000
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LD6806TD/23H from NXP Semiconductors is a 2.3 V fixed-output, 200 mA ultra-low-dropout linear regulator in SOT753 (TSOP5) package, featuring 80 mV typical dropout at full load, 30 µV RMS output noise (10 Hz–100 kHz), and active-HIGH enable with 1.4 V VIH threshold. It delivers stable power to noise-sensitive analog circuitry in space-constrained mobile handsets and portable media players.
For engineers reviewing the LD6806TD/23H datasheet, LD6806TD/23H pinout, LD6806TD/23H application, or LD6806TD/23H equivalent, key selection criteria include its high-ohmic (3-state) output during disable, thermal shutdown at 160 °C, ±0.5 % output voltage accuracy at +25 °C, and compatibility with 1 µF X7R ceramic output capacitors for fast 200 µs startup.
Technical Context
The LD6806TD/23H uses a monolithic silicon LDO architecture with internal reference generator, current limiting, and thermal protection. Its pass transistor operates in linear mode with minimal VIN–VOUT differential-enabling operation down to 2.3 V input while maintaining 2.3 V output regulation across −40 °C to +85 °C ambient.
Enable control is implemented via a dedicated EN pin with 0.4 V VIL and 1.4 V VIH, driving an internal logic stage that places the OUT pin in high-impedance state when disabled-critical for power sequencing in multi-rail systems. PSRR reaches −55 dB at 1 kHz under 30 mA load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.3 V ±2 % over −30 °C to +85 °C; enables direct replacement of 2.3 V logic rails without external feedback. |
| Dropout Voltage | 80 mV typical at 200 mA (SOT753 variant); allows ≥2.38 V input to sustain regulated 2.3 V output-reducing wasted headroom in battery-powered designs. |
| Noise (RMS) | 30 µV over 10 Hz–100 kHz bandwidth; supports low-noise analog signal chains (e.g., ADC references, RF biasing) without additional filtering. |
| PSRR | −55 dB at 1 kHz; suppresses switching noise from upstream DC-DC converters feeding the LDO input. |
| Quiescent Current | 70–100 µA typical at no load; ensures <1 µA shutdown current when EN = LOW-preserving battery life in standby modes. |
| Startup Time | 200 µs to 95 % of 2.3 V; enables rapid power-up of peripherals in wake-from-sleep sequences. |
| Thermal Shutdown | Triggers at 160 °C junction temperature with 20 K hysteresis; prevents permanent damage during sustained overload or poor PCB thermal design. |
Pinout & Package
SOT753 (TSOP5) plastic surface-mounted package: 5-lead gull-wing, 3.0 mm × 2.5 mm × 1.1 mm body, Pb-free/RoHS-compliant, 0.95 mm lead pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (IN) | Input supply voltage | Accepts 2.3 V–5.5 V; requires local 1 µF ceramic decoupling capacitor for stability. |
| 2 (GND) | Ground reference | Low-impedance return path; must connect directly to PCB ground plane to minimize noise coupling. |
| 3 (EN) | Enable control input | Active-HIGH logic interface; drives internal regulator core; 0.4 V max VIL ensures robust noise immunity. |
| 4 (n.c.) | No connection | Internally unconnected; must remain floating-no external tie or pull-up/down required. |
| 5 (OUT) | Regulated output | Delivers 2.3 V ±2 %; high-ohmic (3-state) when EN = LOW-eliminates backfeed into powered-down subsystems. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low dropout | 80 mV at 200 mA enables operation from single Li-ion cell (3.0 V min) while delivering 2.3 V with >700 mV headroom margin. |
| High-ohmic disable | EN = LOW forces OUT into high-Z state-prevents reverse current flow and simplifies power sequencing in multi-voltage domain systems. |
| Low-noise regulation | 30 µV RMS noise supports precision analog circuits (e.g., audio codecs, sensor front-ends) without requiring post-LDO LC filtering. |
| Integrated ESD protection | 10 kV HBM rating on all pins eliminates need for external TVS diodes in handheld device I/O interfaces. |
| Thermal watchdog | 160 °C shutdown with 20 K hysteresis provides fail-safe protection against PCB layout-induced thermal runaway. |
Applications
| Mobile Phone Baseband Power | Portable Media Player Audio Bias |
|---|---|
Use Scenario: Supplying 2.3 V to baseband processor I/O banks in GSM/WCDMA handsets operating from single-cell Li-ion battery. IC Role / Device Role / Timing Role: Primary LDO providing clean, sequenced 2.3 V rail with high-ohmic disable during deep-sleep mode. Use Value: Prevents backfeed into powered-down baseband sections, reducing system leakage current by >95 % versus standard LDOs with pull-down outputs. | Use Scenario: Biasing DAC and headphone amplifier stages in flash-based MP3 players with tight board area constraints. IC Role / Device Role / Timing Role: Low-noise, fast-startup regulator delivering stable 2.3 V to analog signal chain components. Use Value: 30 µV RMS noise avoids audible hiss; 200 µs startup enables instant audio playback after button press-no perceptible delay. |
| Wearable Sensor Hub Core Supply | Bluetooth LE Module I/O Rail |
Use Scenario: Powering ARM Cortex-M0+ microcontroller and MEMS sensor interface in compact fitness trackers. IC Role / Device Role / Timing Role: Main 2.3 V supply enabling low-power active mode and sub-µA shutdown current during motion-sensing idle periods. Use Value: 1.0 µA typical shutdown current extends coin-cell battery life to >12 months in always-on sensing applications. | Use Scenario: Providing 2.3 V logic-level supply to Bluetooth Low Energy SoC GPIO and radio interface circuits. IC Role / Device Role / Timing Role: Regulator ensuring voltage compliance for BLE module's digital I/O while rejecting noise from RF transceiver switching. Use Value: −55 dB PSRR at 1 kHz minimizes digital switching noise coupling into sensitive RF receive paths-improving link budget by ≥3 dB. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6206P232MR-G | 200 mA, 2.3 V fixed, SOT-23-5; 150 mV dropout at 200 mA; no enable pin; no thermal shutdown. | Lacks EN control and thermal protection-requires external enable circuitry and careful thermal design. | Choose only if board space permits SOT-23-5 and system-level enable/thermal management is already implemented. |
| Richtek RT9013-23GB | 300 mA, 2.3 V fixed, SOT-23-5; 250 mV dropout at 300 mA; active-HIGH EN; 1.5 µA quiescent current in shutdown. | Higher current capability but larger dropout and lower PSRR (−45 dB @ 1 kHz); no integrated ESD protection. | Preferable for higher-load applications where 250 mV dropout is acceptable and external ESD protection is available. |
Compared with XC6206P232MR-G and RT9013-23GB, the LD6806TD/23H uniquely combines 80 mV dropout, 30 µV noise, integrated thermal/ESD protection, and high-ohmic disable in a compact SOT753 package-making it optimal for noise-sensitive, space-constrained, and thermally demanding portable electronics.
Availability
LD6806TD/23H is available at Aetrix Electronics and suitable for mobile handset power management, portable audio biasing, wearable sensor hub supplies, and Bluetooth LE module I/O rail applications requiring stable component supply and long-term lifecycle support.
Supply support for LD6806TD/23H includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer electronics.
The LD6806 series belongs to NXP's ultra-low-noise, miniaturized LDO portfolio-designed specifically for power integrity in battery-operated portable devices where board space, thermal performance, and analog signal fidelity are critical.
FAQ
What is the maximum input voltage rating for the LD6806TD/23H?
The LD6806TD/23H has an absolute maximum input voltage of +6.0 V for transient conditions up to 4 ms, with recommended continuous operation between 2.3 V and 5.5 V. Exceeding 6.0 V-even briefly-may cause irreversible damage. For reliable long-term use, maintain VIN ≤ 5.5 V under all operating conditions, including ripple and load-dump transients. The LD6806TD/23H incorporates internal overvoltage protection only at the ESD level (10 kV HBM), not for sustained overvoltage events.
Does the LD6806TD/23H require an external output capacitor, and what type is recommended?
Yes, the LD6806TD/23H requires a minimum 1.0 µF X7R ceramic capacitor at the OUT pin for stability and correct dynamic response. The datasheet specifies 0.7 µF as the absolute minimum, but 1.0 µF is recommended to accommodate ±30 % capacitor tolerance over −40 °C to +125 °C. Tantalum or aluminum electrolytic capacitors are not recommended due to higher ESR, which can degrade PSRR and transient response. The LD6806TD/23H is optimized for low-ESR ceramics (5–500 mΩ).
How does the high-ohmic output state function during disable, and what is its impedance?
When the EN pin is driven LOW (<0.4 V), the LD6806TD/23H disables its internal pass transistor and places the OUT pin in a high-impedance (3-state) condition-effectively disconnecting the output from the internal regulator. This state prevents backfeed current into powered-down downstream circuits. While exact impedance is not specified, the high-ohmic behavior is confirmed by the "LD6806x/xxH" suffix designation and functional block diagram showing open-circuit output during disable. It is not a defined resistance value but a controlled floating state.
What is the thermal resistance (Rth(j-a)) of the LD6806TD/23H in its SOT753 package?
The LD6806TD/23H in SOT753 package has a typical thermal resistance from junction to ambient (Rth(j-a)) of 125 K/W under standard test conditions (Tamb = 25 °C, two-layer PCB). This value assumes optimal PCB layout: solid copper connections on all pins, especially GND, and use of internal ground/power planes as heat spreaders. Actual Rth(j-a) in end applications may vary significantly based on copper area, layer count, and via placement-designers should verify junction temperature using worst-case power dissipation (Pdiss = (VIN − 2.3 V) × IOUT) and measured thermal performance.
Can the LD6806TD/23H be used with input voltages below 2.3 V?
No-the LD6806TD/23H requires a minimum input voltage of 2.3 V to maintain regulation, as specified in the Recommended Operating Conditions table. At input voltages below 2.3 V, the device enters dropout mode and cannot sustain 2.3 V output; output voltage will track VIN minus dropout (e.g., ~2.22 V at VIN = 2.3 V and 200 mA). Operation below 2.3 V is outside specification and may result in unpredictable behavior, including failure to start up or loss of PSRR/noise performance. The 2.3 V lower limit applies across the full −40 °C to +85 °C ambient range.
LD6806TD/23H,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2.3V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.13V @ 200mA
- Current - Output:
- 200mA
- Current - Quiescent (Iq):
- 100 µA
- Current - Supply (Max):
- 250 µA
- PSRR:
- 55dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSOP
LD6806TD/23H,125 FAQ
1.How can I place an order for LD6806TD/23H,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6806TD/23H,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6806TD/23H,125 reliable?
The price and inventory of LD6806TD/23H,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6806TD/23H,125 is usually 5 days.
3.What payment methods are accepted for LD6806TD/23H,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6806TD/23H,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LD6806TD/23H,125?
LD6806TD/23H,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6806TD/23H,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6806TD/23H,125?
For technical support, including LD6806TD/23H,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6806TD/23H,125 requirements.
6.How does Aetrix verify that LD6806TD/23H,125 is sourced from the original manufacturer or authorized distributors?
All LD6806TD/23H,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6806TD/23H,125 meets industry standards.
7.What is the process for return or replacement of LD6806TD/23H,125?
All LD6806TD/23H,125 units undergo pre-shipment inspection (PSI). If there is an issue with LD6806TD/23H,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6806TD/23H,125 part is unused and in its original packaging.
Return procedure for LD6806TD/23H,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LD6806TD/23H,125 Tags
-
MIC5504-1.8YM5-TR
Microchip Technology
-
MIC5504-3.3YM5-TR
Microchip Technology
-
MIC5365-3.0YC5-TR
Microchip Technology
-
MIC5365-1.8YC5-TR
Microchip Technology
-
MIC5365-2.5YC5-TR
Microchip Technology
-
MIC5365-3.3YC5-TR
Microchip Technology
-
MIC5365-3.3YD5-TR
Microchip Technology
-
MIC5317-3.3YM5-TR
Microchip Technology
-
TLV1117LV33DCYR
Texas Instruments
-
MIC5317-3.3YMT-TZ
Microchip Technology
-
MIC5528-3.3YMT-TR
Microchip Technology
-
TLV75801PDRVR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
