NXP Semiconductors LD6815TD/33H,125

Overview

LD6815TD/33H from NXP Semiconductors is a fixed-output 3.3 V, 150 mA low-dropout regulator with ultra-high PSRR (75 dB at 1 kHz), 250 mV dropout at full load, and high-ohmic (3-state) output during disable. It operates from 2.3 V to 5.5 V input and targets power-sensitive portable applications requiring clean, stable voltage rails.

For engineers reviewing the LD6815TD/33H datasheet, LD6815TD/33H pinout, LD6815TD/33H application, or LD6815TD/33H equivalent, this page delivers verified electrical specs, TSOP5 package details, enable-controlled shutdown behavior, RMS noise (40 µV), and real-world selection guidance for smartphone, tablet, and digital camera power management designs.

Technical Context

The LD6815TD/33H implements a PMOS pass transistor architecture enabling low dropout and high PSRR without requiring an external bypass capacitor. Its enable input (EN, active HIGH) controls a high-impedance output state-no pull-down path-making it suitable for systems where output isolation during shutdown is critical.

It features overcurrent protection, 0.1 µA shutdown quiescent current, 6 kV HBM ESD rating, and stable operation with ≥0.7 µF X7R ceramic output capacitance. Thermal resistance is 125 K/W (junction-to-ambient, typical), and startup time is 150 µs under full-load conditions.

Key Specifications

Pinout & Package

SOT753 (TSOP5) plastic surface-mount package: 2.9 × 1.5 × 1.0 mm, 5-pin lead frame, industry-standard footprint with 0.95 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with XC6206P332MR and RT9193-33GB, the LD6815TD/33H uniquely balances ultra-high PSRR, true 3-state disable, and sub-µA shutdown-making it optimal for noise-critical, sequenced portable power domains where rail integrity and system-level isolation are non-negotiable.

Availability

LD6815TD/33H is available at Aetrix Electronics and suitable for smartphone power management, tablet PC core logic supply, and digital still camera sensor bias applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LD6815TD/33H includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer electronics.

The LD6815 series belongs to NXP's high-PSRR LDO portfolio, designed specifically for portable battery-powered devices where noise rejection, low quiescent current, and output isolation during disable are essential for system-level power integrity.

FAQ

What is the output voltage tolerance of the LD6815TD/33H over temperature?

The LD6815TD/33H guarantees ±3% output voltage variation across −40 °C to +85 °C ambient temperature at 1 mA load. At +25 °C, tolerance tightens to ±2% for 3.3 V nominal output, ensuring reliable operation for 3.3 V logic families and interface standards such as SDIO and USB PHY.

Does the LD6815TD/33H require an input capacitor?

Yes-the LD6815TD/33H recommends a 1 µF X7R ceramic capacitor on the IN pin to stabilize the input supply and suppress transient spikes. While not strictly mandatory for basic regulation, omitting it degrades PSRR performance and increases susceptibility to line transients, especially when sourced from switching regulators.

How does the high-ohmic disable mode of the LD6815TD/33H differ from auto-discharge types?

The LD6815TD/33H enters a true high-ohmic (3-state) output during disable-no internal discharge path exists. In contrast, LD6815TD/33P uses an integrated 100 Ω pull-down transistor to actively discharge the output. This makes the LD6815TD/33H ideal for systems where output voltage retention or isolation from downstream loads is required during sleep.

What is the minimum recommended output capacitance for stable operation of the LD6815TD/33H?

The LD6815TD/33H requires a minimum 0.7 µF X7R ceramic capacitor on the OUT pin for guaranteed stability across temperature and load. The recommended value is 1.0 µF, and ESR must be between 5 mΩ and 500 mΩ. Using lower capacitance risks oscillation or degraded transient response.

Can the LD6815TD/33H be used with a 1.8 V enable signal?

Yes-the LD6815TD/33H has a VIH threshold of 1.1 V (min), making it fully compatible with 1.8 V GPIO outputs. With a 1.8 V enable signal, the device achieves full turn-on margin (>0.7 V above VIH), ensuring robust activation even under voltage droop or PCB trace resistance.