NXP Semiconductors LD6815TD/36P,125
- Part No.:
- LD6815TD/36P,125
- Manufacturer:
- NXP Semiconductors
- Package:
- SC-74A, SOT-753
- Datasheet:
-
LD6815TD/36P,125.pdf
- Description:
- NEXPERIA LD6815TD/36P - FIXED PO
- Quantity:
- Payment:

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Product details
Overview
LD6815TD/36P,125 from NXP Semiconductors is a fixed-output 3.6 V, 150 mA low-dropout (LDO) regulator in SOT753 (TSOP5) package, featuring 75 dB PSRR at 1 kHz, 250 mV dropout at full load, and 40 µV RMS output noise (10 Hz–100 kHz). It delivers stable power to noise-sensitive analog and RF circuitry in portable consumer electronics.
For engineers reviewing the LD6815TD/36P,125 datasheet, LD6815TD/36P,125 pinout, LD6815TD/36P,125 application, or LD6815TD/36P,125 equivalent, this page provides verified specifications, validated pin functions, confirmed thermal and noise performance, and real-world mobile device use cases - all aligned with NXP's Rev. 3 product data sheet dated 17 October 2013.
Technical Context
The LD6815TD/36P,125 integrates a high-PSRR bandgap reference, low-noise error amplifier, and PMOS pass transistor optimized for fast transient response and minimal voltage droop under dynamic load. Its auto-discharge function actively pulls down the output during shutdown via a 100 Ω internal pull-down resistor.
Designed for battery-powered systems, it operates across −40 °C to +85 °C ambient, supports input voltages from 2.3 V to 5.5 V, and maintains regulation with only 0.7 µF external output capacitance (X7R, ±30% tolerance). Startup time is 150 µs; shutdown time is 300 µs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output voltage | Fixed 3.6 V ±2% over −40 °C to +85 °C; enables direct powering of 3.3 V–3.6 V logic rails without external feedback. |
| Max output current | 150 mA continuous; sufficient for baseband processors, camera modules, and RF front-end biasing in compact handhelds. |
| Dropout voltage | 250 mV at 150 mA; allows operation from single-cell Li-ion (3.0 V min) while maintaining regulation at full load. |
| PSRR | 75 dB at 1 kHz; suppresses switching noise from DC-DC converters feeding the LDO input, critical for ADCs and PLLs. |
| RMS output noise | 40 µV (10 Hz–100 kHz); ensures clean supply for precision analog sensors and audio codecs without added filtering. |
| Quiescent current | 0.1 µA in shutdown mode; extends battery life in always-on standby states such as RTC or sensor wake-up circuits. |
| Enable threshold | VIH = 1.1 V (min), VIL = 0.4 V (max); compatible with 1.8 V and 3.3 V GPIOs without level-shifting. |
Pinout & Package
SOT753 (TSOP5) plastic surface-mounted package, 2.9 mm × 1.5 mm × 1.0 mm, 5-lead, RoHS-compliant, halogen-free, dark green finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - IN | Regulator input | Accepts 2.3 V–5.5 V unregulated supply; requires ≥0.7 µF ceramic input capacitor for stability. |
| 2 - GND | Supply ground | Common return path for input, output, and enable; must connect to solid ground plane for thermal and noise performance. |
| 3 - EN | Enable control | Active-HIGH digital input; drives regulator into 0.1 µA shutdown when pulled ≤0.4 V; no external pull-up required. |
| 4 - n.c. | No connection | Internally unconnected; must remain floating or tied to GND per layout guidelines - no signal routing allowed. |
| 5 - OUT | Regulated output | Delivers 3.6 V ±2% at up to 150 mA; includes auto-discharge (100 Ω pull-down) when EN = LOW. |
Key Features
| Feature | Design Value |
|---|---|
| High PSRR (75 dB @ 1 kHz) | Enables co-location with noisy DC-DC converters in space-constrained PCBs without compromising analog signal integrity. |
| Auto-discharge output | 100 Ω internal pull-down rapidly discharges output capacitance on disable, preventing unintended wake-up of downstream circuitry. |
| Ultra-low shutdown current (0.1 µA) | Minimizes battery drain in long-duration sleep modes typical of smartphones and IoT edge nodes. |
| 6 kV HBM ESD protection | Meets IEC 61340-3-1 requirements for handling and assembly in standard manufacturing environments. |
| Stable with 0.7 µF X7R output cap | Reduces BOM count and board area vs. legacy LDOs requiring ≥2.2 µF; supports miniaturized 0402/0603 capacitors. |
Applications
| Smartphone Power Management | Tablet PC Audio Subsystem |
|---|---|
Use Scenario: Supplying 3.6 V bias to cellular transceiver RFICs and baseband processors during active call mode. IC Role / Device Role / Timing Role: Primary low-noise post-regulator delivering clean, stable voltage after buck converter stage. Use Value: 75 dB PSRR rejects switching ripple from upstream DC-DC, preserving RF sensitivity and reducing bit error rate. |
Use Scenario: Powering high-resolution DACs and headphone amplifiers in tablet media playback circuits. IC Role / Device Role / Timing Role: Low-noise LDO providing dedicated analog supply rail isolated from digital noise sources. Use Value: 40 µV RMS noise prevents audible hiss and distortion in 24-bit/192 kHz audio paths. |
| Digital Still Camera Sensor Bias | Portable Media Player Display Driver |
Use Scenario: Delivering regulated 3.6 V to CMOS image sensor analog front-end and timing controller. IC Role / Device Role / Timing Role: Precision voltage source ensuring consistent pixel response and low fixed-pattern noise. Use Value: ±2% output accuracy and <250 mV dropout maintain sensor performance across declining battery voltage (3.0–4.2 V). |
Use Scenario: Supplying display driver ICs (e.g., OLED or TFT gate drivers) requiring stable 3.6 V with fast load transient response. IC Role / Device Role / Timing Role: Fast-startup (150 µs) LDO enabling instant screen wake-up from deep sleep. Use Value: Auto-discharge function clears residual charge on display bus lines, eliminating ghosting or flicker on power-up. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS7A0536PDQNR | 3.6 V fixed, 200 mA, 1.4 µA quiescent current (active), 220 mV dropout at 200 mA; SOT-23-5 package. | Higher output current but higher active IQ; lacks auto-discharge; smaller footprint but lower thermal dissipation capability. | Select when higher load margin is needed and shutdown discharge is handled externally. |
| MCP1700T-3602E/TT | 3.6 V fixed, 250 mA, 1.6 µA quiescent current (active), 600 mV dropout at 250 mA; SOT-23-3 package (no EN pin). | No enable control or auto-discharge; higher dropout limits usable input range; simpler 3-pin interface. | Select for cost-sensitive, non-shutdown applications where 3.6 V rail is always active. |
Compared with TPS7A0536PDQNR and MCP1700T-3602E/TT, the LD6815TD/36P,125 uniquely combines ultra-low shutdown IQ (0.1 µA), integrated auto-discharge, and industry-leading 75 dB PSRR in a thermally robust SOT753 package - making it optimal for battery-critical, noise-sensitive mobile subsystems.
Availability
LD6815TD/36P,125 is available at Aetrix Electronics and suitable for smartphone power management, tablet audio subsystems, digital still camera sensor bias, and portable media player display drivers requiring stable component supply, long-term lifecycle support, and guaranteed RoHS/halogen-free compliance.
Supply support for LD6815TD/36P,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and consumer markets.
The LD6815 series belongs to NXP's low-power analog portfolio, designed specifically for high-PSRR, low-noise power regulation in space- and battery-constrained portable electronics - emphasizing efficiency, reliability, and ease of integration.
FAQ
What is the nominal output voltage and tolerance of the LD6815TD/36P,125?
The LD6815TD/36P,125 delivers a fixed nominal output voltage of 3.6 V with a tolerance of ±2% over the full operating temperature range (−40 °C to +85 °C) and load conditions (1 mA to 150 mA). This specification is guaranteed by design and verified per NXP's Rev. 3 product data sheet, ensuring compatibility with 3.3 V–3.6 V logic and analog components without external trimming.
Does the LD6815TD/36P,125 include an auto-discharge function, and how does it operate?
Yes, the LD6815TD/36P,125 implements an auto-discharge function activated when the EN pin is driven LOW. During shutdown, a 100 Ω internal pull-down resistor connects the OUT pin to GND, discharging external output capacitance within 300 µs. This prevents residual voltage from causing unintended behavior in downstream circuitry - a key requirement for reliable power sequencing in smartphones and tablets.
What are the minimum and recommended external capacitor values for stable operation of the LD6815TD/36P,125?
The LD6815TD/36P,125 requires a minimum 0.7 µF X7R ceramic capacitor on the OUT pin for stability, with a recommended value of 1.0 µF (±30% tolerance). An input capacitor of the same value (0.7–1.0 µF) is also recommended on the IN pin. These values ensure proper loop compensation, transient response, and startup/shutdown timing - as validated in NXP's application diagram and electrical characteristics table.
What is the thermal resistance (Rth(j-a)) of the LD6815TD/36P,125, and how does it affect power dissipation?
The LD6815TD/36P,125 has a typical junction-to-ambient thermal resistance (Rth(j-a)) of 125 K/W under standard two-layer PCB conditions. At maximum 150 mA output and 250 mV dropout, power dissipation is 37.5 mW - resulting in a ~4.7 °C junction rise above ambient. Proper PCB layout (solid ground/power planes, thermal vias) is essential to maintain safe operation below the 125 °C max junction temperature limit.
Is the LD6815TD/36P,125 RoHS-compliant and halogen-free, and what does the "Dark Green" designation mean?
Yes, the LD6815TD/36P,125 is fully RoHS-compliant, lead-free, and free of halogens and antimony - meeting NXP's "Dark Green" environmental standard. This designation confirms compliance with stringent regulatory requirements for consumer electronics sold in EU, China, and other regulated markets, and ensures compatibility with lead-free reflow soldering profiles per J-STD-020D.
LD6815TD/36P,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Bulk
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 3.6V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.25V @ 150mA (Typ)
- Current - Output:
- 150mA
- Current - Quiescent (Iq):
- 35 µA
- Current - Supply (Max):
- 150 µA
- PSRR:
- 75dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Transient Voltage
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSOP
LD6815TD/36P,125 FAQ
1.How can I place an order for LD6815TD/36P,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6815TD/36P,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6815TD/36P,125 reliable?
The price and inventory of LD6815TD/36P,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6815TD/36P,125 is usually 5 days.
3.What payment methods are accepted for LD6815TD/36P,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6815TD/36P,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LD6815TD/36P,125?
LD6815TD/36P,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6815TD/36P,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6815TD/36P,125?
For technical support, including LD6815TD/36P,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6815TD/36P,125 requirements.
6.How does Aetrix verify that LD6815TD/36P,125 is sourced from the original manufacturer or authorized distributors?
All LD6815TD/36P,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6815TD/36P,125 meets industry standards.
7.What is the process for return or replacement of LD6815TD/36P,125?
All LD6815TD/36P,125 units undergo pre-shipment inspection (PSI). If there is an issue with LD6815TD/36P,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6815TD/36P,125 part is unused and in its original packaging.
Return procedure for LD6815TD/36P,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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