NXP Semiconductors LD6836TD/20H,125
- Part No.:
- LD6836TD/20H,125
- Manufacturer:
- NXP Semiconductors
- Package:
- SC-74A, SOT-753
- Datasheet:
-
LD6836TD/20H,125.pdf
- Description:
- IC REG LINEAR 2V 300MA 5TSOP
- Quantity:
- Payment:

- Shipping:

Inventory:12,000
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Product details
Overview
LD6836TD/20H,125 from NXP Semiconductors is a fixed-output 2.0 V, 300 mA ultra-low-dropout linear regulator in SOT753 (SOT23-5 compatible) package, featuring 100 mV typical dropout at full load, 30 µV RMS output noise (10 Hz–100 kHz), and active-HIGH enable with 150 µs startup time. It delivers stable power to noise-sensitive analog circuitry in space-constrained portable electronics.
For engineers reviewing the LD6836TD/20H,125 datasheet, LD6836TD/20H,125 pinout, LD6836TD/20H,125 application, or LD6836TD/20H,125 equivalent, key selection criteria include its high-ohmic (3-state) output during disable, ±0.5% output voltage accuracy at 25°C, 55 dB PSRR at 1 kHz, and guaranteed operation across −40°C to +85°C ambient.
Technical Context
The LD6836TD/20H,125 implements a PMOS pass transistor architecture enabling ultra-low dropout and low quiescent current. Its internal bandgap reference, error amplifier, and thermal shutdown circuitry ensure stable regulation under varying line, load, and temperature conditions while maintaining low noise performance.
It operates with input voltages from 2.3 V to 5.5 V and requires only a 1.0 µF ceramic output capacitor for stability. The enable pin (EN) controls device state with VIH ≥ 1.1 V and VIL ≤ 0.4 V, independent of VIN, and the high-ohmic output state eliminates external discharge paths when disabled.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.0 V ±0.5% at 25°C; supports precision biasing of core logic and analog sensors |
| Dropout Voltage | 100 mV typical at 300 mA; enables efficient operation even with tight VIN–VOUT margins |
| PSRR | 55 dB at 1 kHz; suppresses switching noise from upstream DC-DC converters |
| Output Noise | 30 µV RMS (10 Hz–100 kHz); critical for ADC reference, RF LNA, and audio signal chains |
| Quiescent Current | 70–100 µA active; 0.1 µA in shutdown; extends battery life in always-on subsystems |
| Enable Threshold | VIH = 1.1 V min, VIL = 0.4 V max; compatible with 1.8 V and 3.3 V GPIO control |
| Thermal Resistance | Rth(j-a) = 125 K/W; supports continuous 300 mA operation on standard 2-layer PCBs |
Pinout & Package
SOT753 plastic surface-mounted package (5 leads, 1.3 mm × 2.5 mm × 1.1 mm body), compatible with SC-74A footprint and reflow soldering per J-STD-020C MSL1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - IN | Regulator input voltage | Accepts 2.3 V–5.5 V supply; requires local 1 µF input decoupling |
| 2 - GND | Supply ground | Primary return path for input/output currents; must connect to low-impedance ground plane |
| 3 - EN | Enable input (active HIGH) | Drives regulator ON/OFF; 0.1 µA shutdown current when pulled LOW |
| 4 - n.c. | No connection | Internally unconnected; must remain floating or grounded-no external tie |
| 5 - OUT | Regulated output voltage | Delivers 2.0 V @ up to 300 mA; high-ohmic state when EN = LOW |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low dropout | 100 mV typical at 300 mA enables use with Li-ion single-cell (3.0 V min) or boosted 2.5 V rails |
| Low-noise regulation | 30 µV RMS output noise ensures clean power for high-resolution ADCs and RF receivers |
| High-ohmic disable mode | Output floats to preserve downstream bias conditions without external pull-down resistors |
| Integrated protection | Over-temperature shutdown (160°C) and current limiting prevent damage during fault conditions |
| ESD robustness | 10 kV HBM ESD rating simplifies board-level ESD design and improves manufacturing yield |
Applications
| Smartphone Baseband Core Supply | Digital Still Camera Image Sensor Bias |
|---|---|
Use Scenario: Powering ARM Cortex-A series application processor cores requiring tightly regulated 2.0 V with minimal ripple. IC Role / Device Role / Timing Role: Primary LDO delivering clean, low-noise 2.0 V to CPU/GPU voltage domains during dynamic DVFS transitions. Use Value: 150 µs startup time synchronizes with SoC power sequencing; 55 dB PSRR rejects noise from shared PMIC switchers. | Use Scenario: Providing stable bias to CMOS image sensor analog front-end (AFE) and column ADC circuits. IC Role / Device Role / Timing Role: Low-noise post-regulator for sensor analog supply rail, placed close to sensor die. Use Value: 30 µV RMS noise prevents fixed-pattern noise and SNR degradation; high-ohmic disable avoids sensor reset glitches. |
| Portable Media Player Audio DAC Supply | Personal Navigation Device GPS Front-End |
Use Scenario: Supplying 2.0 V to stereo audio DAC and headphone amplifier ICs in battery-powered media players. IC Role / Device Role / Timing Role: Dedicated low-noise LDO for audio signal chain, isolated from noisy digital supplies. Use Value: Ultra-low dropout preserves battery runtime; ±0.5% output accuracy maintains consistent DAC reference scaling. | Use Scenario: Powering GPS RF front-end LNAs and downconverters in handheld navigation units. IC Role / Device Role / Timing Role: Clean 2.0 V supply for GPS receiver analog section, co-located with antenna module. Use Value: 125 K/W thermal resistance allows full 300 mA delivery in compact sealed enclosures; 10 kV HBM withstands handling ESD. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LD6836TD/20P | Pull-down output (100 Ω) instead of high-ohmic; 300 µs shutdown time vs. floating disable | Required where automatic output discharge is needed after disable (e.g., fast system reset) | Select LD6836TD/20P only if auto-discharge is mandatory; otherwise LD6836TD/20H,125 provides lower leakage and simpler bias control |
| Torex XC6219B202MR-G | 200 mA output, 150 mV dropout, 2.0 V fixed, SOT-25 package; no integrated ESD protection | Limited to lower-current analog rails; requires external ESD protection in harsh environments | Use XC6219B202MR-G only in cost-sensitive, low-power applications where 300 mA headroom and 10 kV HBM are not required |
Compared with LD6836TD/20P and XC6219B202MR-G, LD6836TD/20H,125 uniquely combines 300 mA drive capability, 100 mV dropout, 30 µV noise, and 10 kV HBM in a proven SOT753 package-making it optimal for high-reliability portable analog power rails.
Availability
LD6836TD/20H,125 is available at Aetrix Electronics and suitable for smartphone baseband, digital camera sensor, portable audio DAC, GPS front-end, and personal navigation device applications requiring stable component supply and long-term industrial availability.
Supply support for LD6836TD/20H,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company specializing in secure connectivity solutions for automotive, industrial, and consumer electronics, with leadership in power management and analog interface ICs.
The LD6836 series was designed specifically for ultra-miniaturized portable devices demanding low-noise, low-dropout, and high-accuracy regulation in sub-3 mm² footprints-targeting next-generation mobile and wearable platforms.
FAQ
What is the nominal output voltage and tolerance of the LD6836TD/20H,125?
The LD6836TD/20H,125 delivers a fixed 2.0 V output with ±0.5% accuracy at +25°C and ±3% over −30°C to +85°C ambient. This tight tolerance ensures reliable operation of voltage-sensitive analog blocks like ADC references and RF bias networks without external trimming.
Does the LD6836TD/20H,125 require an external output capacitor, and what value is recommended?
Yes, the LD6836TD/20H,125 requires a minimum 0.7 µF ceramic output capacitor (X7R, ±30% tolerance) for stability, with 1.0 µF recommended. The capacitor must have ESR between 5 mΩ and 500 mΩ; insufficient capacitance causes oscillation or slow transient response.
How does the high-ohmic disable mode of the LD6836TD/20H,125 affect system behavior?
When disabled (EN < 0.4 V), the LD6836TD/20H,125 places its OUT pin in a high-impedance (3-state) condition-neither sourcing nor sinking current. This preserves downstream node voltage and avoids unintended discharge paths, unlike pull-down variants such as LD6836TD/20P.
What is the maximum input voltage and thermal limit for continuous operation of the LD6836TD/20H,125?
The LD6836TD/20H,125 supports up to +6.0 V transient input (4 ms) and +5.5 V continuous input. Its junction temperature is rated to +125°C, with thermal shutdown activating at +160°C and 20 K hysteresis-enabling robust operation in sealed portable enclosures with limited airflow.
Is the LD6836TD/20H,125 RoHS-compliant and halogen-free?
Yes, the LD6836TD/20H,125 is Pb-free, RoHS-compliant, and fully halogen- and antimony-free (NXP "dark green" compliance). It meets JEDEC J-STD-020C reflow requirements and carries MSL1 moisture sensitivity rating for uncomplicated assembly.
LD6836TD/20H,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.2V @ 300mA
- Current - Output:
- 300mA
- Current - Quiescent (Iq):
- 100 µA
- Current - Supply (Max):
- 250 µA
- PSRR:
- 55dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-TSOP
LD6836TD/20H,125 FAQ
1.How can I place an order for LD6836TD/20H,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for LD6836TD/20H,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LD6836TD/20H,125 reliable?
The price and inventory of LD6836TD/20H,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LD6836TD/20H,125 is usually 5 days.
3.What payment methods are accepted for LD6836TD/20H,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LD6836TD/20H,125 transactions.
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4.How is shipping managed for LD6836TD/20H,125?
LD6836TD/20H,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LD6836TD/20H,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LD6836TD/20H,125?
For technical support, including LD6836TD/20H,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LD6836TD/20H,125 requirements.
6.How does Aetrix verify that LD6836TD/20H,125 is sourced from the original manufacturer or authorized distributors?
All LD6836TD/20H,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LD6836TD/20H,125 meets industry standards.
7.What is the process for return or replacement of LD6836TD/20H,125?
All LD6836TD/20H,125 units undergo pre-shipment inspection (PSI). If there is an issue with LD6836TD/20H,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LD6836TD/20H,125 part is unused and in its original packaging.
Return procedure for LD6836TD/20H,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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