STMicroelectronics LDH40PURY

Overview

LDH40PURY from STMicroelectronics is an AEC-Q100 Grade 1 qualified adjustable low-dropout linear regulator designed for direct connection to automotive battery rails (up to 40 V input), delivering up to 200 mA with 0.5% output voltage accuracy at 25 °C, 700 mV typical dropout at 200 mA, and ultra-low 2 µA quiescent current at no load. It supports always-on systems in body control modules and ADAS domains.

For engineers reviewing the LDH40PURY datasheet, LDH40PURY pinout, LDH40PURY application, or LDH40PURY equivalent, key selection criteria include its wettable-flank DFN2x2-6L automotive package, Power Good open-drain output (PG pin), logic-controlled shutdown (EN), and active output discharge function-critical for safe power sequencing in safety-critical vehicle subsystems.

Technical Context

The LDH40PURY implements a P-channel MOSFET pass element enabling operation down to 3.3 V input while sustaining 40 V maximum input, accommodating automotive load-dump transients. Its bandgap reference and error amplifier deliver 0.5% initial output accuracy and <±2.5% total variation over –40 °C to +150 °C junction temperature.

Internal protection includes thermal shutdown at 175 °C (20 °C hysteresis), current limiting (350–1000 mA depending on conditions), and an open-drain Power Good flag asserting when VOUT reaches 93–98% of nominal and deasserting at 86–95%. The ADJ pin enables remote sensing via resistor divider for output voltages from 1.2 V to 22 V.

Key Specifications

Pinout & Package

LDH40PURY is supplied in an AEC-Q100 Grade 1 qualified DFN 2×2 mm 6-lead package with wettable flanks (exposed pad), optimized for automated optical inspection (AOI) and high-density PCB layouts in automotive applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar adjustable LDO applications.

Compared with TLD5098EL and TLV73312P, LDH40PURY uniquely combines AEC-Q100 Grade 1 qualification, 40 V input capability, adjustable output with PG flag, and wettable-flank packaging-making it irreplaceable for safety-critical, battery-direct automotive LDO applications requiring design-in longevity and thermal robustness.

Availability

LDH40PURY is available at Aetrix Electronics and suitable for body control modules, ADAS camera ECUs, and infotainment head units requiring stable component supply with full automotive-grade traceability and long-term lifecycle support.

Supply support for LDH40PURY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power management solutions with vertical manufacturing and AEC-Q100-compliant product development.

The LDH40 series belongs to ST's automotive-grade precision LDO portfolio, engineered specifically for direct-battery-connected applications demanding ultra-low quiescent current, extended input range, and functional safety-aware features like Power Good and thermal protection.

FAQ

What is the purpose of the exposed pad on the LDH40PURY DFN package?

The exposed pad on the LDH40PURY's DFN2x2-6L wettable flank package must be soldered to the PCB ground plane. It serves dual functions: lowering thermal resistance (RθJA = 62 °C/W) to sustain 200 mA output at high ambient temperatures, and providing low-impedance grounding for noise-sensitive analog circuitry. Failure to connect it compromises both thermal performance and PSRR.

Can LDH40PURY be used with ceramic output capacitors below 1 µF?

No. The LDH40PURY requires a minimum 1.0 µF ceramic output capacitor (X5R/X7R dielectric) with ESR between 5 mΩ and 10 Ω to ensure loop stability across –40 °C to +150 °C. Capacitors below 1 µF risk oscillation or poor transient response, as confirmed by stability plane analysis in Figures 24–25 of DS14147 Rev 5.

How does the Power Good (PG) pin behave during enable/disable transitions?

The PG pin is high-impedance (Hi-Z) when EN = LOW (device disabled) or when VOUT is within valid regulation range. It pulls low only when VOUT drops below the falling threshold (86–95% VOUT). During startup, PG asserts high only after VOUT reaches 93–98% VOUT and remains stable-providing clean, chatter-free reset signaling without external filtering.

Is the ADJ pin compatible with remote voltage sensing in noisy automotive environments?

Yes. The ADJ pin draws only 0.1–0.5 µA, enabling use of high-value resistor dividers (e.g., R1 = 1 MΩ, R2 = 100 kΩ) that minimize current-induced errors and improve noise immunity. Layout best practices-twisted-pair routing of ADJ and VOUT traces back to the load-allow accurate remote sensing even near high-di/dt switching nodes in ECU designs.