STMicroelectronics LDK120C35R

Overview

LDK120C35R from STMicroelectronics is a 3.5 V fixed-output, 200 mA low-dropout linear regulator with 100 mV typical dropout at 100 mA, 100 µA max quiescent current, and 51 µV_RMS output noise (10 Hz–100 kHz) when using a 10 nF bypass capacitor. It operates from 1.9 V to 5.5 V input, supports logic-controlled shutdown (<1 µA OFF mode), and is stabilized with a 1 µF ceramic output capacitor. It targets power-sensitive RF and analog circuitry in portable battery-powered systems.

For engineers reviewing the LDK120C35R datasheet, LDK120C35R pinout, LDK120C35R application, or LDK120C35R equivalent, key selection criteria include its ultra-low noise performance, guaranteed 200 mA output under 125 °C junction temperature, ±2.0% output voltage tolerance at 25 °C, compatibility with minimal 1 µF ceramic C_OUT, and enable-controlled power sequencing for multi-rail systems.

Technical Context

The LDK120C35R employs a PMOS pass transistor architecture enabling ultra-low dropout and near-zero gate-drive current, eliminating the need for external compensation. Its internal bandgap reference and error amplifier deliver tight load/line regulation (0.006 %/mA and 0.05 %/V) across –40 °C to 125 °C.

It integrates thermal shutdown (160 °C trip, 20 °C hysteresis) and constant-current short-circuit protection (400 mA typical), while the EN pin accepts TTL/CMOS-compatible logic thresholds (V_IL ≤ 0.4 V, V_IH ≥ 1.2 V) across full input and temperature range. The BYP pin on SOT23/SOT323 packages enables optional noise filtering via external 10 nF capacitor.

Key Specifications

Pinout & Package

LDK120C35R is packaged in SOT323-5L - a 1.8 mm × 2.0 mm × 0.9 mm surface-mount package with 0.65 mm lead pitch, optimized for space-constrained portable designs. Pin numbering follows JEDEC standard top-view orientation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-noise LDO applications.

Compared with the LDK120C35R, the XC6210B352MR-G offers lower noise but sacrifices enable control and thermal safety, while the ADP160ACBZ-3.5-R7 delivers superior shutdown IQ and noise at the expense of current capacity and bill-of-materials simplicity.

Availability

LDK120C35R is available at Aetrix Electronics and suitable for wireless sensor nodes, portable medical instrumentation, industrial handheld scanners, and automotive infotainment I/O rails requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LDK120C35R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LDK120 series belongs to ST's high-performance analog power management portfolio, engineered specifically for ultra-low-noise, low-I_Q regulation in space- and battery-constrained portable electronics.

FAQ

What is the minimum input voltage required for 3.5 V output at 200 mA load?

The LDK120C35R requires VIN ≥ VOUT + VDROP = 3.5 V + 300 mV = 3.8 V at 200 mA and 125 °C (max dropout per datasheet Table 4). At 25 °C, 100 mV dropout allows operation down to 3.6 V. Input below 3.6 V risks dropout and output collapse under full load.

Can the BYP pin be left unconnected without affecting stability?

Yes. The BYP pin on LDK120C35R (SOT323-5L) is optional for noise reduction. If unused, it must be left floating with no PCB trace - not tied to GND or OUT. Stability is fully maintained with only 1 µF COUT; the BYP cap reduces noise by ~2× but is not required for loop stability.

Does LDK120C35R support ceramic capacitors larger than 1 µF on the output?

Yes. Datasheet Figure 25 confirms stable operation with COUT up to 22 µF (X5R/X7R ceramic) and ESR as low as 0.01 Ω. Larger values improve transient response and reduce output impedance at high frequencies, but do not degrade phase margin - unlike many older LDOs requiring minimum ESR.

How does thermal shutdown behave during sustained overload?

When junction temperature reaches 160 °C, thermal shutdown activates, disabling the pass transistor and reducing IOUT to near zero. After cooling by ≥20 °C hysteresis, the device automatically resumes regulation without external reset. This protects against permanent damage during continuous short-circuit or excessive ambient temperature.