STMicroelectronics LDK120PU25R

Overview

LDK120PU25R from STMicroelectronics is a 200 mA, 2.5 V fixed-output low-dropout linear regulator with 100 mV typical dropout at 100 mA, 100 µA max quiescent current, ±2.0% output voltage tolerance at 25 °C, and operation from 1.9–5.5 V input. It features logic-controlled shutdown (<1 µA OFF mode), ceramic capacitor compatibility (1 µF COUT), and thermal/short-circuit protection-designed for power-sensitive mobile phone baseband and camera sensor rails.

For engineers reviewing the LDK120PU25R datasheet, LDK120PU25R pinout, LDK120PU25R application, or LDK120PU25R equivalent, key selection criteria include ultra-low noise (51 µVRMS with 10 nF bypass), wide -40 °C to 125 °C junction temperature range, and DFN6 (1.2 × 1.3 mm) package suitability for space-constrained portable PCBs.

Technical Context

The LDK120PU25R employs a PMOS pass transistor architecture enabling ultra-low dropout and near-zero gate-drive current, eliminating external compensation requirements. Its internal bandgap reference and error amplifier deliver tight DC accuracy and high PSRR (55 dB at 120 Hz–10 kHz) without external feedback resistors.

Logic-controlled enable (EN) operates with TTL-compatible thresholds (0.4 V low / 1.2 V high) across full temperature range, while integrated thermal shutdown (160 °C trip, 20 °C hysteresis) and constant-current short-circuit limiting ensure robustness in battery-powered systems with variable load transients.

Key Specifications

Pinout & Package

LDK120PU25R is packaged in a 6-pin DFN (1.2 × 1.3 mm, 0.4 mm pitch) with wettable flanks, optimized for automated optical inspection and high-density layout. Pin 5 is NC and must be connected to GND per ST mechanical data.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with XC6219B251MR-G and RT9013-25GB, LDK120PU25R uniquely balances ultra-low noise (51 µVRMS), minimal dropout (100 mV), and DFN6 footprint-making it optimal for noise-sensitive, space-constrained, single-cell Li-ion applications where both efficiency and signal integrity are critical.

Availability

LDK120PU25R is available at Aetrix Electronics and suitable for mobile phones, digital still cameras, portable medical devices, and industrial handheld terminals requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for LDK120PU25R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LDK120 series belongs to ST's high-performance analog LDO portfolio, engineered specifically for ultra-low-noise, low-quiescent-current power management in battery-powered portable electronics.

FAQ

What is the minimum input voltage required for stable 2.5 V output at 200 mA load?

The LDK120PU25R maintains regulation down to VIN = VOUT + VDROP. At 200 mA and 25 °C, maximum dropout is 300 mV per datasheet Table 4, so minimum input is 2.8 V. At elevated temperatures (125 °C), dropout rises to 300 mV, confirming 2.8 V as the design-minimum for full-load operation across temperature.

Can the BYP pin be left unconnected without affecting stability or noise performance?

Yes-the BYP pin on the fixed-version LDK120PU25R may be left floating if the 10 nF bypass capacitor is omitted. ST explicitly states "if not used the relevant pin must be left floating with no routing on the board." Stability remains assured with only 1 µF COUT, though output noise increases from 51 µVRMS to 148 µVRMS without the bypass cap.

Is the NC pin (Pin 5) required to be grounded in the DFN6 package?

Yes-per ST's mechanical data (Figure 38 and Table 7), Pin 5 is designated NC but must be soldered to GND on the PCB. This is mandatory for thermal dissipation (reducing RthJA by ~15 °C/W) and mechanical reliability; leaving it unconnected violates ST's assembly guidelines and risks solder joint fracture during thermal cycling.

Does the LDK120PU25R support reverse-voltage protection or input overvoltage clamping?

No-the LDK120PU25R lacks integrated reverse-voltage protection or input overvoltage clamping. Absolute maximum VIN is 7 V (Table 2), and operation outside 1.9–5.5 V violates recommended conditions. External protection (e.g., series Schottky diode for reverse polarity, TVS for transients) must be added if system-level faults could expose the IN pin to voltages beyond this range.