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STMicroelectronics LDK120PU30R

Part No.:
LDK120PU30R
Manufacturer:
STMicroelectronics
Category:
Voltage Regulators - Linear, Low Drop Out (LDO) Regulators
Package:
6-XFDFN
Datasheet:
AetrixLDK120PU30R.pdf
Description:
IC REG LINEAR 3V 200MA 6DFN
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:4,236

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Product details

Overview

LDK120PU30R from STMicroelectronics is a 3.0 V fixed-output, 200 mA low-dropout linear regulator with 100 mV typical dropout at 100 mA, 100 µA max quiescent current, ±2.0% output voltage tolerance at 25 °C, and operation from 1.9 V to 5.5 V input. It delivers ultra-low noise (51 µVRMS, 10 Hz–100 kHz, with 10 nF bypass) and logic-controlled shutdown (<1 µA OFF mode), targeting power rails in battery-powered portable electronics.

For engineers reviewing the LDK120PU30R datasheet, LDK120PU30R pinout, LDK120PU30R application, or LDK120PU30R equivalent, key selection criteria include dropout performance under 200 mA load, ceramic-capacitor stability (1 µF COUT), thermal shutdown threshold (160 °C), enable logic thresholds (0.4 V low / 1.2 V high), and compatibility with SOT23-5L/SOT323-5L/DFN6 packages.

Technical Context

The LDK120PU30R implements a PMOS pass transistor architecture enabling ultra-low dropout and minimal quiescent current across temperature. Its internal bandgap reference and error amplifier maintain tight output regulation (±3.0% over –40 °C to 125 °C) while supporting fast load transient response (typ. <50 µs settling for 1 mA → 200 mA step) and robust line regulation (0.05 %/V).

It integrates logic-level enable control with hysteresis-free input thresholds, short-circuit constant-current limiting (~400 mA), and thermal foldback protection triggered at 160 °C with 20 °C hysteresis. The device is stable with 1 µF ceramic output capacitors and supports optional 10 nF bypass capacitance on the BYP pin to reduce output noise by ~65%.

Key Specifications

Parameter Value and Actual Design Meaning
Output Voltage Fixed 3.0 V ±2.0% at 25 °C; ±3.0% over full temperature range - ensures stable MCU core or sensor biasing without external feedback.
Max Output Current 200 mA guaranteed - sufficient for powering single-core microcontrollers, RF transceivers, or imaging sensors in compact portable designs.
Dropout Voltage 100 mV typ. at 100 mA (3.0 V output); ≤300 mV max at 200 mA - enables operation down to 3.1 V input, extending battery runtime in Li-ion/Li-poly systems.
Quiescent Current 60 µA typ. at no load; ≤100 µA max over temperature - minimizes standby power loss in always-on subsystems like real-time clocks or wake-up circuits.
Output Noise 51 µVRMS (10 Hz–100 kHz, with 10 nF BYP cap); 148 µVRMS without - meets stringent noise requirements for ADC references and RF front-end biasing.
PSRR 55 dB (120 Hz–10 kHz, 100 mV ripple) - suppresses switching noise from upstream DC-DC converters feeding the LDO input.
Operating Temp –40 °C to +125 °C junction - qualified for industrial and automotive cabin applications requiring extended thermal margin.

Pinout & Package

LDK120PU30R is packaged in DFN6 (1.2 × 1.3 mm, 0.4 mm height), a space-constrained, thermally enhanced leadless package suitable for high-density portable PCB layouts. Pin 1 is marked by a dot; pin numbering follows standard top-view convention.

Pin/Terminal Circuit Role Design Meaning
1 (IN) Input voltage supply Accepts 1.9–5.5 V DC; requires local 1 µF ceramic decoupling capacitor (CIN) placed adjacent to this pin.
2 (GND) Power ground reference Primary return path for load current and internal circuitry; must be connected to low-impedance system ground plane.
3 (EN) Enable logic input Active-high control: ≥1.2 V = ON, ≤0.4 V = shutdown; draws ≤100 nA; enables system-level power sequencing and sleep-mode control.
4 (BYP/ADJ/NC) Bypass input (fixed version) Optional 10 nF capacitor to GND reduces output noise; if unused, must remain floating-no PCB trace or pull-up/down allowed.
5 (OUT) Regulated output Delivers stable 3.0 V to load; requires 1–22 µF ceramic capacitor (COUT) with ESR ≤10 Ω for stability per datasheet guidelines.
6 (NC) No-connect terminal Internally unconnected; must be tied to GND on PCB for mechanical reliability and thermal conduction in DFN6 package.

Key Features

Feature Design Value
Ultra-low noise with bypass option 51 µVRMS (10 Hz–100 kHz) when 10 nF capacitor added to BYP pin - enables clean analog/RF supply without additional filtering stages.
Ceramic-capacitor stability Stable with 1 µF X5R/X7R ceramic COUT - eliminates need for larger, less reliable tantalum or aluminum electrolytic capacitors.
Logic-compatible enable input VIL ≤ 0.4 V, VIH ≥ 1.2 V across full temperature and input voltage range - directly interfaces with 1.8 V/3.3 V GPIO without level-shifting.
Thermal and short-circuit protection Auto-recovering thermal shutdown at 160 °C (20 °C hysteresis) and constant-current limit (~400 mA) - prevents catastrophic failure during overload or layout-induced thermal stress.
Wide input voltage range 1.9 V to 5.5 V operation - supports direct connection to single-cell Li-ion (2.7–4.2 V), LiFePO4 (2.0–3.6 V), or regulated 3.3 V/5 V rails.

Applications

Mobile Phone Power Management Digital Still Camera Sensor Bias

Use Scenario: Supplying 3.0 V to baseband processor I/O banks and camera interface logic during active call or video capture.

IC Role / Device Role / Timing Role: Primary low-noise post-regulator stepping down from switched-mode 3.6 V rail to meet strict voltage accuracy and ripple requirements of high-speed digital interfaces.

Use Value: 100 µA quiescent current extends standby time; 100 mV dropout preserves headroom as battery discharges below 3.3 V.

Use Scenario: Providing ultra-clean 3.0 V bias to CMOS image sensor analog front-end and ADC reference inputs.

IC Role / Device Role / Timing Role: Low-noise LDO isolating sensitive analog circuitry from noisy digital supply domains and suppressing switching artifacts from DC-DC converters.

Use Value: 51 µVRMS noise (with BYP cap) prevents quantization errors and maintains >10-bit effective resolution in image data.

Personal Digital Assistant (PDA) Core Logic Cordless Phone Baseband IC

Use Scenario: Powering ARM Cortex-M series MCU core and peripherals in handheld PDA with limited PCB area and thermal mass.

IC Role / Device Role / Timing Role: Compact, thermally efficient 3.0 V regulator delivering 200 mA peak current during touchscreen polling and wireless communication bursts.

Use Value: DFN6 (1.2 × 1.3 mm) footprint saves >40% board space vs. SOT23-5L; 237 °C/W RthJA enables passive cooling in sealed enclosures.

Use Scenario: Regulating 3.0 V for DECT/GAP protocol baseband ICs operating continuously in home cordless phone base stations.

IC Role / Device Role / Timing Role: Always-on, high-reliability LDO maintaining voltage accuracy and PSRR across wide ambient temperature swings (0–40 °C ambient, up to 125 °C junction).

Use Value: ±3.0% output tolerance over –40 °C to +125 °C ensures consistent modulation fidelity and bit-error-rate performance across environmental conditions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Alternative Part Technical Difference Application Difference Selection Advice
Torex XC6210B302MR-G Same 3.0 V fixed output, 200 mA rating, but higher 250 mV dropout at 200 mA; 12 µA typical IQ; no BYP pin. Lacks bypass-capable noise reduction; better suited for ultra-low-IQ always-on monitoring nodes than noise-sensitive analog rails. Select when lowest possible quiescent current dominates over noise or dropout performance.
Richtek RT9013-30GB 3.0 V, 300 mA output; 250 mV dropout at 200 mA; 60 µA IQ; includes reverse-current protection; no BYP pin. Higher current capability and reverse-blocking improve robustness in multi-rail systems with shared grounds, but adds 0.15 mm height and larger SOT23-5 footprint. Select when future-proofing for higher load current or preventing backfeed in complex power trees is required.

Compared with XC6210B302MR-G and RT9013-30GB, the LDK120PU30R uniquely balances ultra-low noise (with BYP), minimal dropout (100 mV), and DFN6 space efficiency - making it optimal for size- and noise-constrained portable applications where 200 mA is sufficient.

Availability

LDK120PU30R is available at Aetrix Electronics and suitable for mobile phones, digital still cameras, PDAs, and cordless phone systems requiring stable component supply with guaranteed 200 mA output, low thermal resistance, and long-term production continuity.

Supply support for LDK120PU30R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LDK120 series belongs to ST's precision low-noise LDO portfolio, engineered specifically for battery-powered portable equipment demanding ultra-low IQ, sub-100 mV dropout, and ceramic-capacitor compatibility in miniature packages.

FAQ

What is the minimum input voltage required for 3.0 V output at 200 mA load?

The LDK120PU30R requires VIN ≥ 3.3 V to maintain regulation at 200 mA, based on its maximum dropout voltage of 300 mV (per Table 4). At 100 mA, VIN ≥ 3.1 V suffices due to 100 mV typical dropout. Input below these thresholds causes output collapse proportional to (VIN – VDROP).

Can the BYP pin be left unconnected, or must it be grounded?

The BYP pin must be left floating if unused - neither grounded nor pulled high. Connecting it to GND or VOUT degrades noise performance and may cause instability. Only add a 10 nF capacitor between BYP and GND when ultra-low noise (51 µVRMS) is required; otherwise, omit the capacitor and leave the pin unconnected with no PCB routing.

Is the DFN6 package thermally compatible with reflow-only assembly?

Yes - the DFN6 (1.2 × 1.3 mm) package is qualified for standard Pb-free reflow profiles (JEDEC J-STD-020). Its exposed pad (Pin 6, NC) must be soldered to a thermal pad on the PCB for optimal heat dissipation; ST recommends a 4×4 array of thermal vias to inner ground planes to achieve the specified 237 °C/W RthJA.

Does the LDK120PU30R support reverse current blocking during shutdown?

No - the LDK120PU30R lacks integrated reverse-current protection. When EN = low and VIN > VOUT, reverse current can flow from OUT to IN through the body diode of the PMOS pass transistor. To prevent backfeed, an external Schottky diode in series with the input or a dedicated reverse-blocking controller is required in bidirectional power architectures.

LDK120PU30R Specifications

Product attributes
Attribute value
Manufacturer:
STMicroelectronics
Series:
-
Package/Case:
6-XFDFN
Packaging:
Tape & Reel (TR)
Product Status:
Active
Output Configuration:
Positive
Output Type:
Fixed
Number of Regulators:
1
Voltage - Input (Max):
5.5V
Voltage - Output (Min/Fixed):
3V
Voltage - Output (Max):
-
Voltage Dropout (Max):
0.3V @ 200mA
Current - Output:
200mA
Current - Quiescent (Iq):
60 µA
Current - Supply (Max):
100 µA
PSRR:
55dB (120Hz ~ 10kHz)
Control Features:
Enable
Protection Features:
Over Current, Over Temperature
Operating Temperature:
-40°C ~ 125°C
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
6-DFN (1.2x1.3)

LDK120PU30R FAQ

1.How can I place an order for LDK120PU30R through Aetrix?

Please submit a Request for Quotation (RFQ) for LDK120PU30R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LDK120PU30R reliable?

The price and inventory of LDK120PU30R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LDK120PU30R is usually 5 days.

3.What payment methods are accepted for LDK120PU30R?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LDK120PU30R transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for LDK120PU30R?

LDK120PU30R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LDK120PU30R order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LDK120PU30R?

For technical support, including LDK120PU30R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LDK120PU30R requirements.

6.How does Aetrix verify that LDK120PU30R is sourced from the original manufacturer or authorized distributors?

All LDK120PU30R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LDK120PU30R meets industry standards.

7.What is the process for return or replacement of LDK120PU30R?

All LDK120PU30R units undergo pre-shipment inspection (PSI). If there is an issue with LDK120PU30R, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LDK120PU30R part is unused and in its original packaging.

Return procedure for LDK120PU30R:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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