STMicroelectronics LDK220M36R

Overview

LDK220M36R from STMicroelectronics is a 3.6 V fixed-output, 200 mA low-dropout linear regulator in SOT23-5L package, featuring 100 mV typical dropout at 100 mA, ±2.0% output voltage tolerance at 25 °C, and logic-controlled shutdown with <1 µA off-mode current. It delivers stable power to noise-sensitive analog circuitry in portable consumer electronics.

For engineers reviewing the LDK220M36R datasheet, LDK220M36R pinout, LDK220M36R application, or LDK220M36R equivalent, key selection criteria include dropout voltage under load, quiescent current across temperature, ceramic capacitor compatibility (1 µF), enable threshold behavior, and thermal shutdown hysteresis - all confirmed in DS10219 Rev 7.

Technical Context

The LDK220M36R implements a bandgap-referenced op-amp control loop with internal current limiting and thermal protection. Its enable input directly controls an internal pass transistor gate, enabling fast startup (200 µs) and active output discharge when EN is low.

It supports both fixed-output (e.g., 3.6 V) and adjustable versions via ADJ/NC pin; the M36R variant is fixed 3.6 V, uses SOT23-5L packaging, and excludes ADJ functionality. Output stability is guaranteed with 1 µF ceramic capacitors and ESR ≤1 Ω.

Key Specifications

Pinout & Package

LDK220M36R is supplied in SOT23-5L package (1.45 mm × 1.60 mm × 1.30 mm), optimized for space-constrained PCB layouts and reflow-compatible assembly. Thermal resistance R_thJA = 160 °C/W enables 200 mA operation without external heatsinking at ambient ≤85 °C.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-noise, enable-controlled LDO applications.

Compared with XC6219B362MR-G and AP2204K-3.6TRG1, LDK220M36R uniquely balances ultra-low dropout (100 mV), sub-25 µV_RMS noise, and integrated output discharge - making it optimal for battery-powered, noise-sensitive systems requiring rapid rail shutdown.

Availability

LDK220M36R is available at Aetrix Electronics and suitable for portable medical sensors, smart TV power rails, laptop embedded controllers, and industrial PLC I/O modules requiring stable component supply with full traceability and long-term lifecycle support.

Supply support for LDK220M36R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LDK220 series belongs to ST's high-performance analog LDO portfolio, engineered specifically for battery-powered and noise-critical applications demanding low quiescent current, ceramic-capacitor stability, and robust thermal protection.

FAQ

What is the minimum input voltage required for regulation at 3.6 V output?

The LDK220M36R maintains regulation down to 2.5 V input, but usable headroom depends on load. At 100 mA, only 3.7 V input is needed (3.6 V + 100 mV dropout); at 200 mA, input must be ≥3.9 V to sustain 3.6 V output per DS10219 Table 6.

Can the LDK220M36R be used with a 10 µF aluminum electrolytic output capacitor?

No - the LDK220M36R is optimized for ceramic capacitors (1–22 µF, ESR ≤1 Ω). Aluminum electrolytics typically exceed 10 Ω ESR and cause instability or oscillation. Use only X5R/X7R 1 µF ceramics placed within 3 mm of the OUT and GND pins.

Is the NC pin (Pin 4) required to be grounded or left floating?

Pin 4 is internally unconnected (NC) and must remain floating - no external connection, grounding, or pulling is permitted. Connecting it risks internal damage or unpredictable behavior, as confirmed in Table 1 of DS10219 Rev 7.

How does the output discharge function behave during enable deactivation?

When EN transitions low, an internal 18 Ω discharge path between OUT and GND activates, discharging C_OUT with τ ≈ 18 Ω × 1 µF = 18 µs time constant. This prevents residual voltage from interfering with downstream logic sequencing or causing latch-up in powered-off sections.