My Inquiry
My Account
STMicroelectronics LDL112PT-TR
- Part No.:
- LDL112PT-TR
- Manufacturer:
- STMicroelectronics
- Package:
- TO-252-5, DPAK (4 Leads + Tab), TO-252AD
- Datasheet:
-
LDL112PT-TR.pdf
- Description:
- IC REG LINEAR POS ADJ 1.2A PPAK
- Quantity:
- Payment:
- Shipping:
Inventory:3,051
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LDL112PT-TR from STMicroelectronics is an adjustable low-dropout linear regulator (LDO) delivering up to 1.2 A output current with 300 mV typical dropout at 1 A, ±2.0% output voltage accuracy at 25 °C, and reverse current protection. It operates from 1.6 V to 5.5 V input and supports output voltages from 0.8 V to 5 V (50 mV steps) - ideal for USB-powered devices and battery-powered point-of-load regulation.
For engineers reviewing the LDL112PT-TR datasheet, LDL112PT-TR pinout, LDL112PT-TR application, or LDL112PT-TR equivalent, key selection criteria include its 35 µA no-load quiescent current, logic-controlled shutdown (<1 µA off-mode), ceramic capacitor compatibility (1 µF COUT), thermal/overcurrent protection, and ADJ-pin-based remote sensing capability.
Technical Context
The LDL112PT-TR uses a PMOS pass transistor architecture enabling true reverse current blocking in both on- and off-states, with internal bandgap reference (800 mV nominal at ADJ pin) and error amplifier driving the gate. Its enable logic interface (EN pin) directly controls internal biasing, allowing full shutdown with sub-1 µA total current draw.
Thermal protection triggers at 165 °C junction temperature with 20 °C hysteresis, while current limiting activates at ~1.4–2 A depending on conditions. The ADJ pin provides a stable 800 mV reference (±2% over temperature), enabling precise external resistor-divider-based output setting per VOUT = 0.8 V × (1 + R1/R2).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output current | 1.2 A guaranteed - supports high-current microcontroller cores or FPGA I/O banks without external boost stages. |
| Dropout voltage | 300 mV typ. at 1 A - enables regulation from 3.6 V input to 3.3 V output with only 300 mV headroom. |
| Quiescent current | 35 µA typ. at no load - extends battery life in always-on sensor nodes or standby power rails. |
| Output voltage accuracy | ±2.0% at 25 °C - ensures reliable operation of 1.8 V or 3.3 V digital logic without margining overhead. |
| Input voltage range | 1.6 V to 5.5 V - compatible with single-cell Li-ion (2.7–4.2 V), USB 5 V, and multi-cell alkaline inputs. |
| ADJ pin reference | 800 mV ±2% - enables accurate, temperature-stable output programming via external resistors. |
| Shutdown current | ≤1 µA - meets ultra-low-power system sleep-state requirements (e.g., IoT endpoint deep-sleep modes). |
| Reverse current protection | Active in all states - prevents backfeed from VOUT to VIN during hot-swap, backup supply switchover, or fault conditions. |
Pinout & Package
LDL112PT-TR is supplied in DFN6 (3x3) mm package with exposed thermal pad. The pinout is standardized across DFN6 variants and matches SO8-batwing and PPAK footprints for layout flexibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | LDO input supply | Accepts 1.6–5.5 V; must be decoupled with ≥1 µF ceramic capacitor near pin. |
| GND | Power and signal reference | Common return path; exposed pad must be soldered to PCB ground plane for thermal and electrical performance. |
| EN | Logic enable control | Active-high; <0.35 V = shutdown (<1 µA), >1.4 V = active; floating not allowed. |
| ADJ | Adjustable feedback reference | 800 mV internal reference node; connects to resistor divider for programmable VOUT. |
| VOUT | Regulated output | Delivers up to 1.2 A; requires ≥1 µF ceramic output capacitor for stability. |
| Exposed pad | Thermal and electrical ground | Must be connected to GND plane; critical for thermal resistance (RthJC = 10 °C/W in DFN6 3x3). |
Key Features
| Feature | Design Value |
|---|---|
| Reverse current blocking | Prevents VOUT→VIN backfeed in all operating states - eliminates need for external blocking diode in dual-supply systems. |
| Ultra-low quiescent current | 35 µA typ. at no load - reduces standby power loss by >90% vs. legacy LDOs (>300 µA typical). |
| Ceramic capacitor stability | Stable with 1 µF COUT - avoids costly tantalum or large electrolytic capacitors; simplifies BOM and layout. |
| Adjustable output (0.8–5 V) | Set via external resistor divider on ADJ pin - enables single BOM variant to support multiple voltage rails. |
| Integrated protections | Current limit (~2 A), thermal shutdown (165 °C), and short-circuit foldback - eliminate need for external fault management circuitry. |
| Wide temperature range | -40 °C to +125 °C junction - qualified for automotive cabin, industrial motor control, and outdoor embedded applications. |
Applications
| USB-C Power Delivery Sink Rail | Wearable Sensor Node Core Supply |
|---|---|
|
Use Scenario: Regulating 5 V USB-C PD input down to 1.8 V for MCU, BLE radio, and MEMS sensors. IC Role / Device Role: Primary point-of-load LDO with reverse current isolation during USB disconnect events. Use Value: Eliminates backfeed into USB port during cable removal; 35 µA IQ extends coin-cell life beyond 1 year in sleep mode. |
Use Scenario: Providing clean, low-noise 3.3 V rail from a 3.7 V Li-ion battery to analog front-end and ADC. IC Role / Device Role: Low-noise, high-PSRR LDO with thermal protection during extended sensor acquisition bursts. Use Value: 135 µVRMS noise (10 Hz–100 kHz) preserves ADC SNR; 300 mV dropout maximizes usable battery voltage range. |
| Industrial PLC I/O Module Logic Rail | Smart Home Hub Processor Core |
|
Use Scenario: Generating isolated 2.5 V logic supply for digital isolators and level shifters in 24 V field-side circuits. IC Role / Device Role: Robust, thermally managed LDO tolerant to wide ambient swings (-40 °C to +85 °C). Use Value: RthJA = 55 °C/W (DFN6 3x3) enables 1.2 A operation without heatsink in confined enclosures. |
Use Scenario: Powering ARM Cortex-A53 core at 1.1 V (via external resistor divider) from a 3.3 V intermediate rail. IC Role / Device Role: Adjustable, precision LDO with tight ±2% output tolerance across temperature and load. Use Value: Enables dynamic voltage scaling (DVS); ADJ reference stability ensures core voltage remains within SoC spec limits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar adjustable LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Torex XC6210B332MR-G | Fixed 3.3 V output only; 150 mA max; no ADJ pin or reverse current protection. | Suitable only for low-current fixed-voltage use cases; cannot replace LDL112PT-TR in adjustable or high-current designs. | Select only if output voltage is fixed and load ≤150 mA - not a functional substitute for LDL112PT-TR. |
| Analog Devices ADM7172ACPZ-3.3-R7 | Fixed 3.3 V; 2 A output; lower noise (7 µVRMS); but no reverse current blocking and higher IQ (250 µA). | Better for noise-sensitive RF/analog rails, but unsuitable where backfeed prevention or ultra-low IQ is required. | Choose when PSRR/noise dominates over reverse blocking and standby power - not drop-in for battery-backed systems. |
Compared with XC6210B332MR-G and ADM7172ACPZ-3.3-R7, the LDL112PT-TR uniquely combines adjustability, reverse current protection, and sub-1 µA shutdown - making it irreplaceable in USB-powered, battery-operated, or dual-supply systems requiring bidirectional isolation.
Availability
LDL112PT-TR is available at Aetrix Electronics and suitable for USB-powered devices, battery-powered systems, and low-voltage point-of-load regulation requiring stable component supply, long-lifecycle assurance, and RoHS-compliant packaging.
Supply support for LDL112PT-TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs, with strong focus on industrial, automotive, and consumer applications.
The LDL112 series belongs to ST's high-efficiency, low-quiescent-current LDO portfolio designed specifically for energy-constrained portable and embedded systems requiring robust protection and flexible output configuration.
FAQ
What output voltage range can be set using the ADJ pin?
The LDL112PT-TR supports output voltages from 0.8 V to 5 V in 50 mV increments, calculated as VOUT = 0.8 V × (1 + R1/R2). The ADJ pin maintains a precise 800 mV reference (±2% over -40 °C to +125 °C), enabling stable remote sensing and accurate division ratio implementation with standard 1% resistors.
Does LDL112PT-TR require an input capacitor?
Yes - a minimum 1 µF ceramic capacitor is recommended at VIN to suppress high-frequency noise and stabilize the internal control loop during fast load transients. ST's datasheet specifies CIN = COUT = 1 µF for all electrical characteristics testing, and omitting CIN may cause instability or degraded line regulation under dynamic input conditions.
How does reverse current protection operate during EN = low?
When EN is pulled low, the internal PMOS pass transistor is fully turned off, and both gate and bulk terminals are actively driven to VOUT potential. This creates zero VGS and interrupts all conduction paths from VOUT to VIN - ensuring reverse current remains below 10 nA even if VOUT exceeds VIN by >100 mV, meeting strict backfeed isolation requirements.
Can LDL112PT-TR be used with tantalum or aluminum electrolytic output capacitors?
No - the LDL112PT-TR is optimized for ceramic capacitors (1–10 µF, ESR < 10 mΩ). Tantalum or aluminum electrolytics exhibit higher ESR and capacitance drift, which can destabilize the control loop and cause oscillation or excessive overshoot during load steps. ST's stability analysis (Figure 25) confirms stable operation only within the ceramic-capacitor ESR/COUT region.
LDL112PT-TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- TO-252-5, DPAK (4 Leads + Tab), TO-252AD
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Adjustable
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 4.9V
- Voltage Dropout (Max):
- 0.6V @ 1.2A
- Current - Output:
- 1.2A
- Current - Quiescent (Iq):
- 70 µA
- Current - Supply (Max):
- 400 µA
- PSRR:
- 53dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Reverse Current
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- PPAK
LDL112PT-TR FAQ
1.How can I place an order for LDL112PT-TR through Aetrix?
Please submit a Request for Quotation (RFQ) for LDL112PT-TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LDL112PT-TR reliable?
The price and inventory of LDL112PT-TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LDL112PT-TR is usually 5 days.
3.What payment methods are accepted for LDL112PT-TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LDL112PT-TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LDL112PT-TR?
LDL112PT-TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LDL112PT-TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LDL112PT-TR?
For technical support, including LDL112PT-TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LDL112PT-TR requirements.
6.How does Aetrix verify that LDL112PT-TR is sourced from the original manufacturer or authorized distributors?
All LDL112PT-TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LDL112PT-TR meets industry standards.
7.What is the process for return or replacement of LDL112PT-TR?
All LDL112PT-TR units undergo pre-shipment inspection (PSI). If there is an issue with LDL112PT-TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LDL112PT-TR part is unused and in its original packaging.
Return procedure for LDL112PT-TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LDL112PT-TR Tags
-
MIC5504-1.8YM5-TR
Microchip Technology
-
MIC5504-3.3YM5-TR
Microchip Technology
-
MIC5365-3.0YC5-TR
Microchip Technology
-
MIC5365-1.8YC5-TR
Microchip Technology
-
MIC5365-2.5YC5-TR
Microchip Technology
-
MIC5365-3.3YC5-TR
Microchip Technology
-
MIC5365-3.3YD5-TR
Microchip Technology
-
MIC5317-3.3YM5-TR
Microchip Technology
-
TLV1117LV33DCYR
Texas Instruments
-
MIC5317-3.3YMT-TZ
Microchip Technology
-
MIC5528-3.3YMT-TR
Microchip Technology
-
TLV75801PDRVR
Texas Instruments
Tech Hub
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…
Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…
Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.
18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…
