STMicroelectronics LDL112PVR

Overview

LDL112PVR from STMicroelectronics is an adjustable low-dropout linear regulator (LDO) delivering up to 1.2 A output current with 300 mV typical dropout at 1 A, ±2.0% output voltage accuracy at 25 °C, and reverse current protection. It operates from 1.6 V to 5.5 V input and supports output voltages from 0.8 V to 5 V in 50 mV steps-ideal for USB-powered devices and battery-powered point-of-load regulation.

For engineers reviewing the LDL112PVR datasheet, LDL112PVR pinout, LDL112PVR application, or LDL112PVR equivalent, this page provides verified technical context, validated pin functions, confirmed thermal and protection behavior, and real-world application constraints-including ceramic capacitor compatibility (1 µF), enable-controlled shutdown (<1 µA off-mode current), and ADJ-pin-based remote sensing capability.

Technical Context

The LDL112PVR uses a PMOS pass transistor architecture enabling true reverse current blocking across all operating states-off-mode, on-mode with overvoltage, and transient conditions-by dynamically switching gate and bulk to VOUT when reverse bias occurs. Its internal bandgap reference (800 mV nominal at ADJ pin) feeds an error amplifier that regulates output via resistor divider feedback.

Thermal shutdown activates at 165 °C with 20 °C hysteresis, and current limiting clamps short-circuit output to 1.4–2 A. The device supports stable operation with 1 µF ceramic output capacitors due to internal compensation optimized for low-ESR ceramics, eliminating need for external compensation networks.

Key Specifications

Pinout & Package

LDL112PVR is available in DFN6 (3x3) mm, DFN6 (2x2) mm, SO8-batwing, and PPAK packages. All variants feature identical pin functionality and thermal performance scaling per package type.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar adjustable LDO applications.

Compared with XC6219B332MR-G and ADM7172ACPZ-3.3-R7, LDL112PVR uniquely combines adjustable output, reverse current protection, 1.2 A capability, and ceramic-capacitor stability in compact DFN6 packages-making it optimal for space-constrained, multi-rail battery systems requiring rail isolation and flexibility.

Availability

LDL112PVR is available at Aetrix Electronics and suitable for USB-powered devices, battery management subsystems, industrial sensor nodes, and low-voltage FPGA I/O banks requiring stable component supply across automotive (-40 °C to 125 °C), medical, and industrial temperature grades.

Supply support for LDL112PVR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets since 1987.

The LDL112 series belongs to ST's high-efficiency, low-quiescent-current LDO portfolio-engineered specifically for battery-powered and energy-conscious applications demanding reverse current blocking, wide input range, and ceramic capacitor compatibility.

FAQ

What is the minimum input voltage required for LDL112PVR to regulate a 1.2 V output?

The minimum input voltage is determined by dropout: V_IN(min) = V_OUT + V_DROP. At 1.2 A load and 125 °C, V_DROP reaches 600 mV (max), so V_IN(min) = 1.2 V + 0.6 V = 1.8 V. At room temperature and light load, 1.6 V input suffices per absolute ratings, but regulation requires ≥1.8 V for 1.2 V output at full current.

Can LDL112PVR be used with an output capacitor smaller than 1 µF?

No-ST specifies 1 µF as the minimum stable output capacitance. Using <1 µF risks oscillation or poor transient response, as the internal compensation is optimized for ≥1 µF ceramic capacitors with ESR <10 mΩ. The datasheet explicitly prohibits smaller values in Section 7's stability plot (Figure 25).

Does LDL112PVR provide output discharge when disabled?

Output discharge is optional and not implemented in the standard LDL112PVR variant. The datasheet notes "(*) The output discharge function is optional" in Figure 2, and ordering code LDL112PVR does not include discharge circuitry. Discharge functionality requires a specific suffix (not present here) and adds ~10 µA quiescent current in shutdown.

How does reverse current protection behave when VOUT exceeds VIN by more than 100 mV?

When VOUT > VIN + 100 mV, the PMOS pass transistor is fully turned off: gate and bulk are actively switched to VOUT, breaking all conduction paths. This occurs in both EN=low (shutdown) and EN=high (active) states-verified in Section 6.3 of DS10321, which defines three distinct blocking conditions covering all operational scenarios.