STMicroelectronics LDLN015PU10R

Overview

LDLN015PU10R from STMicroelectronics is a 150 mA ultra-low-noise linear voltage regulator with fixed 1.0 V output, 6.3 µV_RMS noise (10 Hz–100 kHz), 86 mV typical dropout at 150 mA, and ±1% output accuracy at 25 °C. It operates from 2.1 V to 5.5 V input, supports ceramic output capacitors down to 0.47 µF, and features logic-controlled enable for <2 µA shutdown current - deployed in precision analog power rails for ADCs and RF VCOs.

For engineers reviewing the LDLN015PU10R datasheet, LDLN015PU10R pinout, LDLN015PU10R application, or LDLN015PU10R equivalent, key selection criteria include ultra-low noise performance, PSRR >90 dB at 1 kHz, thermal/short-circuit protection, DFN6 (2 × 2 mm) package compatibility, and no-bypass-capacitor operation in space-constrained battery-powered systems.

Technical Context

The LDLN015PU10R implements a low-dropout linear regulation architecture with internal PMOS pass transistor, enabling stable 1.0 V output under 150 mA load with only 86 mV headroom. Its noise-filtering design achieves 6.3 µV_RMS across 10 Hz–100 kHz without external bypass capacitance.

PSRR exceeds 90 dB below 1 kHz and remains >50 dB up to 100 kHz; enable control uses TTL-compatible thresholds (V_EN(H) ≥ 0.9 V, V_EN(L) ≤ 0.4 V) with 110 µs turn-on time and integrated thermal shutdown at 166 °C with 10 °C hysteresis.

Key Specifications

Pinout & Package

LDLN015PU10R is housed in a thermally enhanced DFN6 (2 × 2 mm) package with exposed pad electrically connected to GND for improved heat dissipation and EMI performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6210B102MR-G and ADP125ARHZ-1.0-R7, LDLN015PU10R uniquely combines sub-10 µV_RMS noise, 35 µA quiescent current, integrated enable, and DFN6 size - making it optimal for miniaturized, battery-sensitive RF/analog subsystems where noise and power efficiency are co-critical.

Availability

LDLN015PU10R is available at Aetrix Electronics and suitable for portable medical devices, wireless sensor networks, industrial PLC I/O modules, and RF front-end power supplies requiring stable component supply and long-term lifecycle support.

Supply support for LDLN015PU10R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, analog chips, and MEMS sensors for industrial, automotive, and consumer markets.

The LDLN015 series belongs to ST's ultra-low-noise LDO product line, engineered specifically for powering noise-sensitive analog and RF circuitry in battery-operated and space-constrained applications.

FAQ

What is the minimum input voltage required for LDLN015PU10R to regulate 1.0 V output at full 150 mA load?

The minimum input voltage is determined by dropout: 1.0 V + 86 mV = 1.086 V. However, the datasheet specifies absolute minimum VIN as 2.1 V for guaranteed operation across temperature and process variation. Below 2.1 V, regulation is not assured even if dropout margin appears sufficient.

Can LDLN015PU10R operate stably with a 0.22 µF ceramic output capacitor?

No. The stability region defined in Figure 15 requires COUT ≥ 0.33 µF. A 0.22 µF capacitor falls outside the stable range and may cause oscillation or poor transient response. Use 0.47 µF or higher for guaranteed stability per ST's characterization.

Is the exposed thermal pad on the DFN6 package required to be soldered to PCB ground?

Yes. The exposed pad is electrically connected to GND and serves as the primary thermal conduction path. ST recommends connecting it to a minimum 100 mm² copper pour via ≥4 thermal vias to maximize heat dissipation and maintain junction temperature within -40 °C to 125 °C limits.

Does LDLN015PU10R require an input capacitor, and if so, what value is recommended?

Yes - a 0.47 µF X5R/X7R ceramic capacitor is recommended at the IN pin, placed as close as possible to pins 1 and 4. This minimizes high-frequency impedance and prevents instability due to PCB trace inductance, especially during load transients.