STMicroelectronics LDLN015PU15R

Overview

LDLN015PU15R from STMicroelectronics is an ultra-low-noise, high-PSRR linear voltage regulator delivering 150 mA output at fixed 1.5 V with ±1% accuracy, 6.3 µV_RMS noise (10 Hz–100 kHz), and 86 mV typical dropout. It operates from 2.1–5.5 V input, features logic-controlled shutdown (I_Q < 2 µA off), and is stable with 0.47 µF ceramic output capacitor-used in precision analog power rails for ADCs and RF VCOs.

For engineers reviewing the LDLN015PU15R datasheet, LDLN015PU15R pinout, LDLN015PU15R application, or LDLN015PU15R equivalent, key selection criteria include output noise floor, PSRR above 90 dB at 1 kHz, thermal shutdown threshold (166 °C), enable logic thresholds (0.4 V low / 0.9 V high), and DFN6 (2 × 2 mm) package compatibility with space-constrained portable designs.

Technical Context

The LDLN015PU15R employs a bandgap-referenced LDO architecture with internal current limiting and thermal foldback protection. Its ultra-low noise stems from optimized internal biasing and filtering, eliminating need for external bypass capacitors.

PSRR exceeds 90 dB below 10 kHz and remains >50 dB up to 100 kHz; enable functionality supports precise system-level power sequencing with 110 µs turn-on time and nanoscale enable pin leakage (<100 nA).

Key Specifications

Pinout & Package

Package: DFN6 (2 × 2 mm), exposed pad electrically connected to GND for thermal and electrical performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6215B152MR-G and ADP160ACBZ-1.5-R7, LDLN015PU15R delivers the lowest noise (6.3 µV_RMS) and lowest dropout (86 mV) in its class-critical for battery-powered precision analog systems where headroom and SNR are constrained.

Availability

LDLN015PU15R is available at Aetrix Electronics and suitable for portable medical devices, RF front-ends, wearable sensors, and industrial data loggers requiring stable component supply and long-term manufacturability.

Supply support for LDLN015PU15R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and analog components for industrial, automotive, and consumer markets.

The LDLN015 series belongs to ST's ultra-low-noise LDO portfolio, engineered specifically for noise-sensitive analog and RF subsystems in battery-operated portable electronics where PSRR, quiescent current, and small-footprint packaging are critical.

FAQ

What is the minimum input voltage required for stable 1.5 V output at full 150 mA load?

The minimum input voltage is calculated as V_OUT + V_DROP = 1.5 V + 0.18 V = 1.68 V per datasheet max dropout, but ST specifies guaranteed operation only down to 2.1 V input. Below 2.1 V, regulation, PSRR, and noise performance are not assured-even if dropout appears sufficient-due to internal biasing constraints.

Can LDLN015PU15R be used with a 10 µF tantalum output capacitor?

No. The device is characterized and guaranteed stable only with ceramic capacitors ranging from 0.33 µF to 4.7 µF. Tantalum capacitors exhibit higher ESR and different frequency response, which may cause instability or excessive overshoot during load transients-violating the stability criteria defined in Figure 15 of the datasheet.

Is the exposed thermal pad on the DFN6 package required to be soldered to PCB ground?

Yes. The exposed pad is electrically connected to GND and serves as the primary thermal conduction path. ST recommends soldering it to a minimum 100 mm² copper pour tied to internal/external GND planes. Omitting this compromises thermal resistance (R_thJA rises from 105 °C/W to >150 °C/W), increasing junction temperature and triggering premature thermal shutdown under load.

Does the enable pin require a pull-up resistor for reliable startup?

No external pull-up is required. The EN pin has no internal pull-up; however, the device powers up enabled only if EN is actively driven ≥0.9 V at power-on. In systems where EN is controlled by an open-drain GPIO or undetermined state at reset, a 100 kΩ pull-up to VIN or system VCC is recommended to ensure predictable initialization and avoid undefined output behavior.