STMicroelectronics LDLN015PU18R

Overview

LDLN015PU18R from STMicroelectronics is a 150 mA ultra-low-noise linear voltage regulator with fixed 1.8 V output, 6.3 µV_RMS noise (10 Hz–100 kHz), 86 mV typical dropout at 150 mA, ±1% output accuracy at 25 °C, and operation from 2.1 V to 5.5 V input. It delivers clean power to noise-sensitive analog circuitry in portable RF systems.

For engineers reviewing the LDLN015PU18R datasheet, LDLN015PU18R pinout, LDLN015PU18R application, or LDLN015PU18R equivalent, key selection criteria include PSRR >90 dB at 1 kHz, 35 µA quiescent current at no load, ceramic-capacitor stability (0.47 µF), logic-controlled shutdown (<2 µA off-mode current), and DFN6 (2 × 2 mm) thermal performance (R_thJA = 105 °C/W).

Technical Context

The LDLN015PU18R employs a PMOS pass transistor architecture enabling low dropout and high PSRR without external bypass capacitors. Its bandgap reference and error amplifier are optimized for sub-10 µV_RMS integrated noise and minimal load/line regulation drift (0.001 %/mA, 0.005 %/V).

Enable control uses TTL-compatible thresholds (V_EN(H) ≥ 0.9 V, V_EN(L) ≤ 0.4 V), with 110 µs turn-on time and internal thermal shutdown at 166 °C. Short-circuit protection limits output current to 300 mA while maintaining GND-referenced exposed pad for thermal dissipation.

Key Specifications

Pinout & Package

Package: DFN6 (2 mm × 2 mm, 0.6 mm height), thermally enhanced with exposed GND pad. RoHS-compliant, ECOPACK®2 grade.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-noise LDO applications.

Compared with XC6210B182MR-G and ADP125ARHZ-1.8-R7, LDLN015PU18R uniquely combines sub-10 µV_RMS noise, >90 dB PSRR up to 10 kHz, and 86 mV dropout-making it optimal for RF and high-resolution data acquisition where spectral purity and efficiency coexist.

Availability

LDLN015PU18R is available at Aetrix Electronics and suitable for mobile RF front-end power, portable medical sensors, wearable audio CODECs, and industrial IoT edge nodes requiring stable component supply across multi-year production cycles.

Supply support for LDLN015PU18R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing silicon solutions for automotive, industrial, and consumer markets.

The LDLN015 series belongs to ST's ultra-low-noise LDO portfolio, engineered specifically for powering noise-critical analog blocks-including RF VCOs, high-speed ADCs, and precision sensor interfaces-in space-constrained portable electronics.

FAQ

What is the minimum input voltage required for stable 1.8 V output at full 150 mA load?

The LDLN015PU18R requires VIN ≥ 1.886 V (1.8 V + 86 mV typical dropout) for stable regulation at 150 mA. Per datasheet Section 4, minimum specified VIN is 2.1 V across temperature and process variation-ensuring margin for worst-case dropout (180 mV max) and line regulation.

Can the device operate without an output capacitor?

No. The LDLN015PU18R requires a minimum 0.33 µF ceramic output capacitor for stability, with 0.47 µF recommended. Omitting C_OUT causes oscillation and violates absolute maximum ratings; no bypass capacitor is needed, but C_OUT is mandatory per Figure 15 (Stability Area) and Table 5.

Is the exposed thermal pad internally connected, and how should it be handled on PCB?

Yes, the exposed pad is electrically connected to GND. It must be soldered to a dedicated GND copper pour using ≥4 thermal vias (0.3 mm diameter) to inner ground planes. Per Figure 25, the recommended footprint includes a 1.4 mm × 1.4 mm thermal pad with solder mask defined to maximize thermal transfer and minimize junction temperature rise.

How does the enable pin behave under slow-rising input signals?

The EN pin has no internal Schmitt trigger; its logic thresholds are fixed at 0.4 V (low) and 0.9 V (high). With slow-rising edges (<100 mV/µs), the device may enter metastable state near threshold, causing erratic turn-on. A pull-up resistor (10–100 kΩ) to VIN and RC filter (10 kΩ + 100 pF) is recommended to ensure clean transitions and avoid intermediate conduction.